DRAM Rank Training via Cross-Rank Code Loading and Voltage Generation
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Solution Overview
Problem
The increasing demand for high-performance and high-capacity memories in mobile devices, such as smartphones and tablets, poses challenges in securing the integrity of data exchanged between application processors and dynamic random access memory (DRAM), particularly due to limitations in loading and setting operation parameters of the DRAM, especially with rank interleaving modes.
Innovation Solution
An electronic device and training method that includes a system-on-chip and a memory device with multiple ranks, where the system-on-chip loads a training code onto one rank and performs training operations on the other ranks, generating reference voltages for sampling output data based on the training results, thereby optimizing data integrity through disabling rank interleaving or adjusting interleaving unit sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rank interleaving mode is used to access DRAM, then access efficiency is improved, but data integrity deteriorates due to characteristic differences across ranks
Solution Approach 1:
The patent applies local quality by generating separate reference voltages for each rank (first reference voltage for first rank, second reference voltage for second rank) based on their individual training results. This allows each rank to be optimized locally for its specific characteristics while maintaining the overall rank interleaved access mode, thereby preserving both access efficiency and data integrity.
2Reliability
If training code size is increased to provide higher performance and reliability, then data integrity is improved, but SRAM capacity requirements increase causing excessive cost
Solution Approach 1:
The patent extracts the training code from SRAM and loads it into DRAM for execution. By moving the training code storage from SRAM to DRAM, the system maintains the ability to perform comprehensive training for high data integrity while avoiding the excessive cost and complexity of increasing SRAM capacity.
3Device complexity
If training code is loaded to DRAM to reduce costs, then SRAM capacity is reduced, but fine setting of operation parameters is prevented due to rank interleaving limitations
Solution Approach 1:
The patent changes the operational parameters by disabling rank interleaving mode specifically during the training phase, allowing the training code to be loaded and executed on a single rank. This parameter change enables fine setting of operation parameters when needed, while the system can revert to rank interleaved mode for normal operation to maintain cost efficiency.
Data Source
AI summary
An electronic device includes a memory device including first and second ranks, and a system-on-chip that exchanges data with the memory device. The system-on-chip loads a first training code to the first rank and performs a first training operation on the second rank using the first training code loaded to the first rank, and loads the first training code to the second rank and performs a second training operation on the first rank using the first training code loaded to the second rank. The system-on-chip generates a first reference voltage for sampling output data of the first rank, and generates a second reference voltage for sampling output data of the second rank. The first and second reference voltages are generated based on a first result of performing the first training operation on the second rank, and a second result of performing the second training operation on the first rank.