DRAM Redundant Word Line Refresh Circuit
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Solution Overview
Problem
Existing DRAM circuits are unable to effectively determine when a redundant word line needs to be refreshed, leading to the row hammer issue where data stored in DRAM cells controlled by these lines can be flipped, rendering them unusable and resulting in inefficient usage and high area costs.
Innovation Solution
A DRAM circuit with a redundant refresh circuit that includes a latch, shift circuit, and multiplexers to determine when a redundant word line needs to be refreshed based on the activation of adjacent word lines, allowing for efficient use of redundant word lines by replacing damaged or overactivated lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If redundant word lines are used to replace activated lines, then area costs are reduced, but the row hammer issue causes data flipping that renders them unusable
Solution Approach 1:
The patent applies preliminary action by refreshing the first and third redundant word lines before they can be affected by row hammer issues from activating the second redundant word line. The refresh circuit detects when the second redundant word line is activated and proactively refreshes the adjacent first and third redundant word lines, preventing data flipping before it occurs.
Solution Approach 2:
The patent applies preliminary anti-action by implementing a refresh mechanism that counteracts the potential row hammer effect before it can damage the redundant word lines. When the second redundant word line is activated, the system immediately triggers a refresh of the first and third redundant word lines, creating a protective action that prevents the harmful data flipping effect.
2Productivity
If the second redundant word line is activated to replace the normal word line, then efficiency is improved, but adjacent redundant word lines become vulnerable to row hammer effects
Solution Approach 1:
The patent applies feedback by implementing a detection mechanism that monitors when the second redundant word line is activated. This feedback signal triggers the refresh circuit to automatically refresh the first and third redundant word lines, creating a closed-loop system that responds to activation events and maintains reliability without sacrificing efficiency.
3Reliability
If traditional refresh mechanisms are used, then normal word lines are refreshed, but redundant word lines cannot be determined to need refreshing
Solution Approach 1:
The patent applies universality by designing a refresh circuit that serves both normal and redundant word lines. The refresh circuit is configured to receive activation signals for redundant word lines and automatically determine when adjacent redundant word lines need refreshing, making the refresh mechanism universally applicable to both normal and redundant word line scenarios.
Data Source
AI summary
A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.