DRAM Refresh Address Control Circuit for Row Hammer Mitigation
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Solution Overview
Problem
In semiconductor memory devices, particularly DRAM, the 'row hammer' effect causes increased data degradation in nearby memory cells due to repeated access, necessitating targeted refreshes that are not efficiently integrated with regular periodic refreshes.
Innovation Solution
A semiconductor memory device that includes a refresh address control circuit to monitor access counts and rates, scheduling targeted refreshes by 'stealing' timing slots from auto-refresh operations when access thresholds are exceeded, thereby identifying and refreshing victim rows affected by the row hammer effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If targeted refreshes are performed frequently to address row hammer effects, then data fidelity in victim rows is improved, but refresh operation overhead and interference with auto-refresh timing increases
Solution Approach 1:
The refresh timing is made dynamic by allowing targeted refreshes to 'steal' timing slots from auto-refresh operations when row hammer activity is detected. The refresh address control circuit dynamically adjusts the refresh schedule based on monitored access patterns, enabling timely targeted refreshes while maintaining overall refresh coverage through adaptive timing slot allocation.
Solution Approach 2:
The system performs preliminary monitoring of access counts to victim rows before scheduling targeted refreshes. By continuously tracking access patterns and identifying row hammer activity in advance, the system can proactively schedule targeted refreshes at appropriate timing slots, preventing data degradation before it occurs while maintaining efficient refresh operation scheduling.
2Reliability
If targeted refreshes are scheduled to occur frequently, then data degradation in victim rows is reduced, but the complexity of managing refresh timing slots increases
Solution Approach 1:
The refresh address control circuit performs multiple functions: it monitors access counts to victim rows, generates targeted refresh addresses, and manages timing slot allocation for both auto-refresh and targeted refresh operations. This multi-functional approach consolidates refresh management complexity into a single control unit that handles both regular and targeted refresh scheduling through unified timing slot management.
Solution Approach 2:
The refresh address control circuit autonomously monitors access patterns and self-adjusts the refresh schedule without external intervention. When row hammer activity is detected, the circuit automatically steals timing slots from auto-refresh operations to perform targeted refreshes, and independently manages the coordination between different refresh types, reducing the need for complex external timing management.
3Productivity
If access monitoring is continuously performed to identify row hammer effects, then targeted refresh scheduling is improved, but the overhead for detecting and measuring access patterns increases
Solution Approach 1:
The refresh address control circuit continuously monitors access counts to victim rows and uses this feedback to dynamically adjust refresh scheduling. When the monitored access count exceeds a threshold indicating row hammer activity, the circuit responds by stealing timing slots to perform targeted refreshes. This feedback mechanism enables efficient targeted refresh scheduling based on real-time access pattern detection without requiring complex continuous analysis.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.