DRAM Refresh Address Generator Segments Normal and Redundancy Cell Rows
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Solution Overview
Problem
Dynamic random-access memory (DRAM) systems face data retention characteristic degradation due to frequent access of redundancy memory cells, which can disturb adjacent cells, leading to reduced data retention times.
Innovation Solution
A semiconductor memory device with a refresh address generator that differentiates refresh cycles for normal and redundancy memory cells, allowing for tailored refresh operations to prevent disturbance and maintain data integrity, including the use of parity bits for defective cell repair and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory cells are frequently accessed to replace defective cells, then data retention characteristics of the DRAM system are maintained, but adjacent redundancy memory cells are disturbed leading to degraded data retention characteristics
Solution Approach 1:
The patent segments the memory cell array into normal memory cell rows and redundancy memory cell rows, applying different refresh strategies to each segment. Normal memory cell rows are refreshed at standard intervals while redundancy memory cell rows are refreshed at extended intervals, thereby isolating the disturbance effects and preventing propagation to adjacent cells.
Solution Approach 2:
The patent applies local quality by implementing location-specific refresh characteristics: redundancy memory cell rows that are frequently accessed receive extended refresh intervals tailored to their specific access patterns and disturbance profiles, while normal memory cell rows maintain standard refresh intervals. This localized adaptation optimizes data retention for each region based on its operational characteristics.
2Reliability
If refresh operations are performed at standard intervals for all memory cells, then normal memory cell data retention is maintained, but redundancy memory cell data retention characteristics are degraded due to frequent access
Solution Approach 1:
The patent implements dynamic refresh interval adjustment based on memory cell type and access characteristics. The refresh control logic dynamically determines extended refresh intervals for redundancy memory cell rows compared to normal memory cell rows, adapting the refresh timing to the specific operational patterns and disturbance susceptibility of each cell type.
Solution Approach 2:
The patent changes the refresh interval parameter specifically for redundancy memory cell rows, extending it beyond the standard refresh interval used for normal memory cells. This parameter modification allows redundancy cells to maintain data retention despite frequent access patterns that would otherwise cause disturbance and data loss at standard refresh intervals.
Data Source
AI summary
Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.