DRAM Row Hammer Refresh Circuit Skipping Defective Cells
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Solution Overview
Problem
Dynamic random access memory (DRAM) refresh operations consume significant power, which is a concern in low power applications, as they are necessary to maintain stored data but can lead to increased energy usage.
Innovation Solution
The implementation of a semiconductor device with a refresh control circuit that selectively skips refresh operations for defective or unused memory cells by mapping them to redundant arrays, reducing unnecessary power consumption by avoiding refresh operations on non-functional memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all memory cells to maintain stored data, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating between functional and non-functional memory cells. The refresh control circuit selectively performs refresh operations only on functional memory cells while skipping defective or unused cells. This is achieved by mapping defective cells to redundant arrays and identifying unused cells through address comparison, thereby applying refresh operations locally only where needed rather than uniformly across all memory cells.
Solution Approach 2:
The patent segments the memory array into functional and non-functional portions. By dividing the refresh operation into selective segments (only refreshing functional cells), the system avoids unnecessary power consumption on defective or unused cells while maintaining data integrity in operational memory regions.
2Reliability
If refresh operations are performed on all memory cells, then data integrity is maintained, but unnecessary power consumption occurs on defective or unused cells
Solution Approach 1:
The patent discards refresh operations on defective and unused memory cells by mapping them to redundant arrays and identifying them through address comparison. The refresh control circuit recovers energy by skipping these unnecessary operations, thereby reducing power consumption without compromising data integrity in functional memory cells.
3Use of energy by moving object
If selective refresh skipping is implemented for defective cells, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a refresh control circuit as an intermediary between the refresh command and the memory array. This intermediary component manages the complexity of selective refresh by handling address comparison, defective cell identification, and redundant array mapping, thereby shielding the rest of the system from complexity while enabling power-efficient selective refreshing.
4Loss of energy
If mapping to redundant arrays is used to skip defective cells, then power consumption is reduced by avoiding refresh on non-functional cells, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-mapping defective cell addresses to redundant array addresses before refresh operations occur. The refresh control circuit compares refresh addresses against a list of defective addresses and pre-determines which cells should be skipped, thereby simplifying the refresh execution process and reducing power consumption without requiring complex real-time decision-making during operation.
Data Source
AI summary
Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.