DRAM Row Control Circuit for Target-Row Refresh

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Solution Overview

Problem

In DRAM memory devices, the information retention time of certain memory cells can be reduced due to repeated access, leading to potential data loss if the refresh command frequency does not align with the memory cell access history, and the use of target-row refresh operations may result in erroneous operations if unused redundant word lines with micro short-circuits are selected.

Innovation Solution

The semiconductor device employs a row control circuit with address detection and boundary detection circuits to identify and manage normal and redundant word lines, ensuring that target-row refresh operations are executed correctly by distinguishing between functional and non-functional redundant word lines, thereby preventing data corruption from micro short-circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If target-row refresh operation is carried out without considering redundant word line usage status, then refresh coverage is improved, but data integrity deteriorates due to micro short-circuits in unused redundant word lines

Engineering Contradiction:
Improveinformation retentionVSAvoiddata corruption from micro short-circuits
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by detecting the usage status of redundant word lines before executing target-row refresh operations. The row control circuit identifies whether redundant word lines are currently being used for normal operations, and only selects them as refresh targets when they are unused. This preliminary detection prevents the harmful effect of micro short-circuits in unused redundant word lines from corrupting data during refresh operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously monitoring the usage status of redundant word lines and using this information to dynamically adjust refresh operations. The row control circuit receives feedback about which word lines are currently active versus unused, and adjusts its target-row refresh selection accordingly. This feedback mechanism ensures that refresh operations maintain high coverage while avoiding unused redundant word lines that could cause data corruption through micro short-circuits.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If all word lines are refreshed at fixed frequency, then refresh simplicity is maintained, but information retention for frequently accessed memory cells deteriorates

Engineering Contradiction:
Improverefresh operation simplicityVSAvoidinformation retention time
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies dynamics by transitioning from static, fixed-frequency refresh operations to dynamic, adaptive target-row refresh operations. Instead of refreshing all word lines at predetermined intervals regardless of access patterns, the system dynamically identifies word lines that require refresh based on actual usage status and access history. This dynamic approach maintains ease of operation through automated detection while significantly improving information retention for frequently accessed memory cells.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the refresh operation parameters based on detected word line usage status. The row control circuit changes the target row parameter dynamically, selecting different word lines for refresh based on current operational needs. This parameter adaptation allows the system to maintain simple automated operation while optimizing information retention by focusing refresh operations on word lines that actually need them.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10867660B2Apparatus and methods for controlling refresh operations
Publication Date: 2020.12.15 MICRON TECHNOLOGY INC
  • US10867660B2 patent drawing
  • US10867660B2 patent drawing
  • US10867660B2 patent drawing

AI summary

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.