DRAM Row Decoder Testing via Leakage Mode and XOR Detection
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Solution Overview
Problem
Existing methods for testing Dynamic Random Access Memory (DRAM) row decoders fail to detect errors when two adjacent columns are simultaneously turned on, leading to data leakage and undetected errors in memory arrays.
Innovation Solution
A method involving writing first and second data into memory cells, enabling a leakage mode to simulate column turn-on conditions, and using an exclusive-OR test mode to determine if multiple columns are simultaneously active, thereby identifying row decoder failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DRAM testing methods are used, then the testing process is simple, but row decoder errors involving simultaneous column turn-ons cannot be detected
Solution Approach 1:
The patent applies preliminary action by pre-configuring the memory array with specific data patterns (first data and second data) and enabling data mask mode before initiating the actual test. This preparation allows the leakage mode to effectively detect simultaneous column turn-ons without requiring complex real-time analysis during testing.
Solution Approach 2:
The patent introduces a leakage mode as an intermediary testing mechanism that simulates column turn-on conditions and enables detection of data leakage between simultaneously activated columns. This intermediary mode bridges the gap between simple memory operations and complex error detection requirements.
2Reliability
If data mask mode is enabled to prevent data leakage, then data integrity is maintained, but the ability to detect simultaneous column activation is reduced
Solution Approach 1:
The patent applies dynamics by dynamically switching between data mask mode and leakage mode during the testing process. The data mask mode is enabled during normal operations to maintain data integrity, while the leakage mode is activated specifically for detection purposes, allowing the system to adapt its behavior based on testing requirements.
Solution Approach 2:
The patent implements periodic action by alternating between masking operations and leakage detection operations in a structured sequence. This periodic switching allows the system to maintain data integrity during most operations while periodically performing detection to identify simultaneous column turn-ons.
3Reliability
If leakage mode is enabled to detect simultaneous column turn-ons, then error detection capability is improved, but the testing time increases due to preset leakage time requirement
Solution Approach 1:
The patent applies parameter changes by adjusting the leakage time parameter to optimize the balance between detection accuracy and testing duration. The preset leakage time is carefully selected to be sufficient for detecting simultaneous column turn-ons while minimizing the overall testing time impact.
Data Source
AI summary
Provided are a method for testing a memory, an apparatus for testing a memory, a computer-readable storage medium, and an electronic device, which relate to the field of integrated circuit technology. The method for testing a memory includes: writing first data into each of memory cells of a memory array; enabling a data mask mode, and writing second data into each of the memory cells of the memory array; enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the memory array; and after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing, to determine whether there are at least two columns simultaneously turned on in the memory array. This method may test whether a row decoder fails.