DRAM Scrubbing Control Circuit for Error Correction
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Solution Overview
Problem
The increasing bit errors and decreasing yield of DRAMs due to shrinking fabrication design rules necessitate improved credibility and performance in semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit, and a control logic circuit that performs scrubbing operations on memory cell rows to correct error bits and prevent their accumulation, enhancing data reliability and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase storage capacity, then memory density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent performs scrubbing operations proactively on memory cell rows before errors accumulate to uncorrectable levels. The counter circuit tracks the number of refresh operations, and when a threshold is reached, the scrubbing operation is triggered to detect and correct errors in advance, preventing future data loss despite continued miniaturization.
Solution Approach 2:
The patent implements a feedback mechanism where the counter circuit monitors refresh operation counts and triggers scrubbing operations based on accumulated usage patterns. This feedback loop allows the system to adaptively maintain data integrity by performing corrections at optimal intervals, ensuring reliability continues to improve even as fabrication rules shrink.
2Reliability
If scrubbing operations are performed frequently to correct errors, then data reliability is improved, but power consumption and operation time increase
Solution Approach 1:
The patent implements periodic scrubbing operations triggered by a counter that monitors the number of refresh operations. Instead of continuous scrubbing, the system performs scrubbing at predetermined intervals (when the counter reaches a threshold value), thereby maintaining data reliability while significantly reducing power consumption compared to continuous error correction operations.
Solution Approach 2:
The patent performs scrubbing operations on selected memory cell rows based on counter thresholds rather than continuously monitoring all rows. This partial action approach applies error correction only when and where needed, reducing overall power consumption while maintaining sufficient data integrity for the memory system's operational requirements.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.