DRAM Selective Self-Refresh for Power Management
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Solution Overview
Problem
Current power management techniques, such as ACPI sleep states, consume significant power due to DRAM and voltage regulator usage, necessitating a method to reduce power consumption during sleep states without compromising system restore times.
Innovation Solution
Implementing a DRAM selective self-refresh operation by generating a retained page map to identify memory pages for retention, relocating these pages within DRAM, and maintaining a subset of memory devices in a self-refresh sleep state, thereby reducing power consumption and allowing for efficient system restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If all memory devices are maintained in active state to preserve system context information, then system restore time is reduced, but power consumption increases significantly
Solution Approach 1:
The patent segments the memory system into active and self-refresh portions. Specifically, it divides DRAM devices into those that remain fully active (containing frequently accessed or critical system context) and those that enter self-refresh mode (containing less frequently accessed data). This segmentation allows the system to preserve necessary context information while reducing overall power consumption during sleep states.
Solution Approach 2:
The patent applies local quality by differentiating the operational state of different memory regions based on their specific requirements. Critical system context information is maintained in actively powered memory regions with full access speed, while less critical data is stored in memory regions operating in self-refresh mode. This localized differentiation optimizes both restore time and power consumption by matching memory state to data importance.
2Use of energy by moving object
If all memory devices are placed in self-refresh mode to reduce power consumption, then power usage decreases, but system restore time increases
Solution Approach 1:
The patent segments the memory system into active and self-refresh portions. Specifically, it divides DRAM devices into those that remain fully active (containing frequently accessed or critical system context) and those that enter self-refresh mode (containing less frequently accessed data). This segmentation allows the system to preserve necessary context information while reducing overall power consumption during sleep states.
Solution Approach 2:
The patent applies local quality by differentiating the operational state of different memory regions based on their specific requirements. Critical system context information is maintained in actively powered memory regions with full access speed, while less critical data is stored in memory regions operating in self-refresh mode. This localized differentiation optimizes both restore time and power consumption by matching memory state to data importance.
3Reliability
If voltage regulator is maintained active to support DRAM power during sleep state, then DRAM data is preserved, but overall platform power consumption increases
Solution Approach 1:
The patent extracts the voltage regulator from the mandatory active state by introducing self-refresh mode for portions of the DRAM system. By taking out the requirement for continuous full-power voltage regulation and replacing it with periodic refresh operations, the system can preserve DRAM data while allowing the voltage regulator to operate at reduced power levels or be completely powered down during sleep states.
Solution Approach 2:
The patent implements periodic action through self-refresh mode, where memory devices perform periodic refresh operations instead of requiring continuous power supply. This periodic refreshing maintains data integrity in DRAM cells while allowing the voltage regulator and other support circuitry to consume significantly less power compared to continuous active operation, thus resolving the contradiction between data preservation and power consumption.
Data Source
AI summary
In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.