DRAM Self-Refresh Abort Mechanism for Fast Exit

Solution Overview

Problem

Current DRAM devices require a significant wait period (tXS) for the memory controller to issue commands after a self-refresh cycle, which increases with device density, leading to inefficiencies in data access and refresh operations.

Innovation Solution

Enabling the DRAM device to abort a self-refresh mode, allowing the memory controller to issue commands sooner by using a 'fast exit' mechanism, where the DRAM device can exit self-refresh mode upon receiving a signal from the memory controller, reducing the wait time from tRFC plus a guard band to tRC plus a guard band.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DRAM device executes a complete self-refresh cycle to ensure all rows are refreshed, then data validity is maintained, but the memory controller must wait for the entire tRFC period (160-550 ns depending on density) before issuing commands

Engineering Contradiction:

Improvedata validityVSAvoidcontroller wait time (tXS)

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a partial refresh of only the first subset of rows before the complete self-refresh cycle would normally finish. This allows the memory controller to exit self-refresh mode and issue commands earlier (after tRC + guard band instead of full tRFC), while still maintaining data validity through the subsequent completion of the full refresh cycle. The preliminary partial refresh ensures critical rows are refreshed early enough to allow controller operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the refresh operation into two distinct phases: a first subset of rows refreshed during the partial refresh operation that enables early exit, and a second subset of rows refreshed during the completion of the full self-refresh cycle. This segmentation allows the controller to operate during the time the second subset is being refreshed, effectively overlapping controller activity with refresh operations and reducing overall wait time.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If DRAM device density increases to provide more storage capacity, then storage capacity is improved, but the self-refresh cycle time (tRFC) approximately doubles, increasing controller wait time

Engineering Contradiction:

Improvestorage capacityVSAvoidcontroller wait time (tXS)

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a partial refresh of only the first subset of rows before the complete self-refresh cycle would normally finish. This allows the memory controller to exit self-refresh mode and issue commands earlier (after tRC + guard band instead of full tRFC), while still maintaining data validity through the subsequent completion of the full refresh cycle. The preliminary partial refresh ensures critical rows are refreshed early enough to allow controller operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the refresh operation into two distinct phases: a first subset of rows refreshed during the partial refresh operation that enables early exit, and a second subset of rows refreshed during the completion of the full self-refresh cycle. This segmentation allows the controller to operate during the time the second subset is being refreshed, effectively overlapping controller activity with refresh operations and reducing overall wait time.

Inventive Principle:

Principle #1Segmentation

3Reliability

If the memory controller waits for the complete refresh cycle (tRFC + guard band) before issuing commands, then data integrity is ensured, but data access efficiency decreases due to increased wait time

Engineering Contradiction:

Improvedata integrityVSAvoiddata access efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing a partial refresh of only the first subset of rows before the complete self-refresh cycle would normally finish. This allows the memory controller to exit self-refresh mode and issue commands earlier (after tRC + guard band instead of full tRFC), while still maintaining data validity through the subsequent completion of the full refresh cycle. The preliminary partial refresh ensures critical rows are refreshed early enough to allow controller operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the refresh operation into two distinct phases: a first subset of rows refreshed during the partial refresh operation that enables early exit, and a second subset of rows refreshed during the completion of the full self-refresh cycle. This segmentation allows the controller to operate during the time the second subset is being refreshed, effectively overlapping controller activity with refresh operations and reducing overall wait time.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9460773B2Fast exit from DRAM self-refresh

Publication Date: 2016.10.04 INTEL CORP

AI summary

Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.