DRAM Sensing Bitline Isolation Logic
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) architectures face challenges with noise interference and packing density, leading to increased access time and potential read errors in open bitline architectures, and inefficient packing in folded bitline architectures, while also consuming high power.
Innovation Solution
An open bitline dynamic memory array architecture is developed where bitlines are selectively connected to either a sense amplifier or a reference voltage during read operations, with every third bitline connected to the voltage supply, reducing crosstalk noise and allowing for efficient packing density without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If open bitline architecture is used, then packing density is improved, but crosstalk noise increases
Solution Approach 1:
The bitline array is segmented into multiple independent groups, with each group containing a subset of bitlines that are selectively activated. During any given sensing operation, only one group is active while other groups remain inactive with their bitlines held at reference voltage, effectively isolating active bitlines from crosstalk while maintaining high packing density through the overall array structure.
Solution Approach 2:
Different regions of the bitline array have different operational states - active regions where sensing occurs and inactive regions where bitlines are held at reference voltage. This local differentiation allows active bitlines to operate with minimal interference while inactive bitlines provide electromagnetic shielding, resolving the crosstalk issue without sacrificing packing density.
2Productivity
If all bitlines are sensed concurrently, then productivity is improved, but crosstalk noise increases
Solution Approach 1:
The sensing operation is divided into periodic time slots, with each time slot dedicated to sensing a specific group of bitlines. Bitlines are activated and sensed in sequential groups rather than all simultaneously, reducing crosstalk within each time slot while maintaining high overall productivity through the periodic cycling through multiple groups.
Solution Approach 2:
The complete set of bitlines is divided into multiple subgroups that are sensed in sequence. Each subgroup contains a manageable number of bitlines that can be sensed concurrently with minimal crosstalk, and the sequential activation of different subgroups maintains high throughput while eliminating the crosstalk problem of sensing all bitlines at once.
3Reliability
If larger capacitors are used to mitigate crosstalk, then reliability is improved, but area increases
Solution Approach 1:
The crosstalk mitigation function is extracted from the capacitor and implemented through the bitline grouping and selective activation mechanism. By removing active bitlines from the electromagnetic environment during sensing operations, the system achieves high read accuracy without requiring larger capacitors, thus maintaining small cell area.
Solution Approach 2:
Inactive bitlines held at reference voltage serve as intermediary elements that provide electromagnetic shielding for active bitlines. This intermediary approach reduces crosstalk and improves read accuracy without requiring changes to the storage capacitor size, maintaining area efficiency.
Data Source
AI summary
A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.