DRAM Array With Shared Source-Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random access memory (DRAM) cells with oxide semiconductor field effect transistors (OSFETs) face challenges in data storage time due to low on-current and off-current, requiring frequent refresh operations and difficulty in reducing power consumption, while also needing modified layouts to increase density.
Innovation Solution
An array of DRAM cells is designed with memory cell pairs in alternating rows, where each pair includes two OSFETs and one capacitor, with bit line contacts electrically coupling common S/D regions to bit lines, allowing for compact arrangement and increased density without affecting substrate device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If oxide semiconductor field effect transistors (OSFETs) are used to extend data storing time, then leakage current is reduced and data storing time is increased, but on-current becomes 10^10 times less than conventional FET making data hard to be read out
Solution Approach 1:
The patent combines OSFETs with conventional FETs in a hybrid configuration where OSFETs are used for storage nodes requiring low leakage, while conventional FETs are used for bit line connections requiring high drive current. This merging allows the system to simultaneously achieve low leakage current for extended data retention and sufficient on-current for efficient data readout.
Solution Approach 2:
Different transistor types are strategically placed in different locations within the memory cell based on functional requirements. OSFETs are positioned at storage nodes where low off-current is critical, while conventional FETs are positioned at bit line interfaces where high on-current is essential. This local differentiation optimizes performance for each specific function.
2Power
If conventional FETs are used, then on-current is high enabling efficient data readout, but off-current is high causing short data storing time and frequent refresh operations
Solution Approach 1:
The patent merges conventional FETs and OSFETs in a single memory cell structure, allowing each transistor type to contribute its strengths. Conventional FETs provide high on-current for efficient readout operations, while OSFETs provide low off-current for extended data retention, eliminating the need for frequent refresh operations.
Solution Approach 2:
The invention applies different transistor technologies to different functional regions: conventional FETs are used where high current drive is needed (bit line connections), while OSFETs are used where low leakage is critical (storage nodes). This spatial differentiation resolves the contradiction between readout efficiency and data retention.
3Quantity of substance
If more memory cells are packed into unit area to increase density, then storage capacity increases, but layout complexity increases and substrate device density may be affected
Solution Approach 1:
The patent merges memory cell pairs from adjacent rows by sharing common source/drain regions and bit line contacts. This consolidation reduces the total number of discrete components, simplifies the layout, and enables higher cell density without proportionally increasing layout complexity.
Solution Approach 2:
The common source/drain regions serve multiple functions: they act as source or drain for multiple transistors within the merged cell pairs, and they provide shared connection points for bit line contacts. This multi-functionality reduces the number of separate components needed, simplifying the overall layout.
4Quantity of substance
If memory cell pairs from different rows share common S/D regions, then device density increases and layout is simplified, but electrical coupling complexity increases
Solution Approach 1:
The common source/drain regions are designed to serve multiple transistors simultaneously, acting as shared electrical nodes. This universal design allows multiple memory cell pairs to be electrically coupled through the same physical structures, simplifying the overall coupling architecture despite the increased number of connections.
Solution Approach 2:
The memory array is segmented into merged cell pairs that share common components. By organizing the structure this way, the electrical coupling is systematically managed through defined shared nodes, making the complexity tractable and the layout more compact.
Data Source
AI summary
An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.