DRAM Shield Plates with Voids for Interference Suppression

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Solution Overview

Problem

Current memory technologies face challenges in scaling integrated circuitry to higher levels of integration while maintaining effective interference suppression and ON current performance in DRAM arrays.

Innovation Solution

Incorporating conductive shield material between memory cells with voids to suppress interference and improve ON current, using a method that involves forming islands of semiconductor material, depositing conductive shield material, and creating voids between the shield material and channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conductive shield material is placed directly adjacent to channel regions, then interference suppression is improved, but ON current performance deteriorates due to excessive shielding effect

Engineering Contradiction:

Improveinterference suppressionVSAvoidON current performance

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies local quality by creating voids (empty spaces) in specific locations between the conductive shield material and channel regions, while maintaining shield material in other areas. This localized modification allows the shield to suppress interference where needed while leaving ON current pathways unobstructed, resolving the contradiction between interference suppression and ON current performance

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent introduces a porous structure by forming voids within the insulative material between the shield and channel regions. This porous configuration allows electromagnetic interference to be blocked by the conductive shield while permitting electrical field lines to pass through the voids to reach the channel regions, thereby maintaining ON current performance

Inventive Principle:

Principle #31Porous materials

2Productivity

If memory cells are scaled to higher integration levels, then device density is improved, but interference between neighboring cells increases

Engineering Contradiction:

Improvedevice densityVSAvoidinterference between cells

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements nesting by placing voids within the insulative material structure between the shield and channel regions. This nested configuration allows the voids to be embedded within existing material layers, providing interference suppression functionality without adding external structure that would increase device footprint, thus maintaining high integration density while reducing interference

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces voids as an intermediary element between the conductive shield material and the channel regions. These voids act as a mediator that allows the shield to perform its interference suppression function while preventing direct contact that would otherwise block electrical fields and reduce ON current, thereby enabling high-density integration with reduced cell-to-cell interference

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses interference and enhances ON current performance by at least 10-fold compared to configurations without voids, enabling better integration and performance in DRAM arrays.

Implementation Method 1

Incorporating conductive shield material between memory cells with voids to suppress interference

Methodology Applied

Scientific EffectElectromagnetic shielding: Faraday Cage

Implementation Method 2

creating voids between the shield material and channel regions... improve ON current

Methodology Applied

Scientific EffectCapacitive coupling reduction: Capacitance

Data Source

PatentUS11217588B2Integrated assemblies comprising voids between active regions and conductive shield plates, and methods of forming integrated assemblies

Publication Date: 2022.01.04 MICRON TECHNOLOGY INC

AI summary

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.