DRAM Stack Capacitor Bottom Cell Plate Wafer Bow Reduction
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Solution Overview
Problem
The challenge in increasing memory cell density in DRAMs is maintaining high storage capacitance while decreasing cell area, and existing methods face issues with wafer bow, cost, and throughput due to thick conductive layers required for forming bottom cell plates in stacked capacitors.
Innovation Solution
A method involving the use of two conductive layers with different deposition methods to form bottom cell plates, eliminating the need for a thick conductive layer, which reduces wafer bow and associated costs, and improves throughput by using a sacrificial layer and chemical mechanical polishing to create voids and expose the patterned sacrificial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick conductive layer is used to form bottom cell plates in stacked capacitors, then the storage capacitance is maintained, but wafer bow increases and manufacturing cost increases
Solution Approach 1:
The bottom cell plate is segmented into multiple thin conductive layers (first conductive layer and second conductive layer) instead of using a single thick conductive layer. Each layer is deposited conformally on the sacrificial layer and in the openings, with the second layer sealing the openings to form voids. This segmentation maintains the required capacitance while reducing wafer bow and improving manufacturing efficiency.
2Reliability
If a thick conductive layer is used to form bottom cell plates, then storage capacitance is maintained, but manufacturing throughput decreases
Solution Approach 1:
The thick conductive layer is divided into multiple thin layers deposited in sequence, allowing for better process control and faster deposition rates without compromising the total capacitance. The conformal deposition method enables parallel processing and reduces the time required for each deposition step.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary structure that enables the formation of the bottom cell plate without requiring a thick conductive layer. The sacrificial layer is patterned with openings, and the conductive layers are deposited conformally on it. After deposition, the sacrificial layer is removed to form voids, completing the bottom cell plate structure.
3Reliability
If a thick conductive layer is used to form bottom cell plates, then storage capacitance is maintained, but manufacturing cost increases
Solution Approach 1:
The bottom cell plate is formed using multiple thin conductive layers instead of a single thick layer, reducing material consumption and deposition costs. The segmented structure allows for more efficient use of conductive materials and reduces the overall manufacturing cost while maintaining the required capacitance.
Solution Approach 2:
A sacrificial layer is used as a temporary, disposable structure that facilitates the formation of the bottom cell plate but is later removed. This sacrificial layer enables the creation of voids and the desired structure without requiring expensive thick conductive layer deposition, thereby reducing manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of stacked capacitors with reduced wafer bow and cost, increased throughput, and improved alignment, enabling higher memory cell density without the need for thick conductive layers.
Implementation Method 1
forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein
Implementation Method 2
removing a portion of the first and second conductive layers to expose the patterned sacrificial layer
Data Source
AI summary
The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.