DRAM Sub-Bank Architecture for Simultaneous Access and Refresh
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) capacitors require periodic refresh operations to maintain data integrity, during which they cannot perform access operations, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A memory chip design with multiple sub-banks within a memory bank, where one sub-bank performs an access operation while the other sub-bank performs a refresh operation simultaneously, allowing for continuous data output and storage by selectively enabling and disabling paths between memory cells and access lines based on address decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory bank performs refresh operations, then data integrity is maintained, but access operations must be paused leading to reduced productivity
Solution Approach 1:
The memory bank is divided into multiple sub-banks (first sub-bank and second sub-bank), each capable of independent operation. This segmentation allows one sub-bank to perform refresh operations while another simultaneously performs access operations, resolving the contradiction between maintaining data integrity and preserving access efficiency.
Solution Approach 2:
By enabling simultaneous refresh and access operations in different sub-banks, the system ensures continuous useful action without interruption. The access operation continues uninterrupted while refresh operations proceed in parallel, eliminating the pause that would normally occur during refresh cycles.
2Device complexity
If multiple sub-banks share common access lines, then device complexity is reduced, but path selection control becomes more challenging
Solution Approach 1:
A control circuit acts as an intermediary between the address decoder and the multiple sub-banks. This control circuit receives decoded row and column addresses and selectively activates appropriate paths (first path or second path) based on the address information, managing the complexity of path selection while sharing common access lines.
Solution Approach 2:
The control circuit dynamically switches between different paths (first path and second path) based on real-time address decoding results. This dynamic path selection allows the system to adaptively route signals to the correct sub-bank, managing the complexity of multiple shared access lines through flexible, condition-based control.
Data Source
AI summary
A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.