DRAM Sub-Channel Architecture for Energy-Efficient Memory Access
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Solution Overview
Problem
Current DRAM technologies face challenges in achieving high bandwidth without significant increases in power consumption, particularly due to energy-intensive row activations and low spatial locality in memory access patterns, which limits bandwidth utilization and increases energy costs.
Innovation Solution
The introduction of a DRAM sub-channel architecture that partitions each bank into multiple sub-channels, allowing for fine-grained row activation and parallel operation, reducing row energy consumption and maintaining bandwidth utilization through Master Wordline Segmentation and data reordering mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DRAM bandwidth optimization is used, then aggregate memory bandwidth increases, but power consumption increases significantly
Solution Approach 1:
The patent divides each DRAM bank into multiple sub-channels (e.g., 4 sub-channels per bank), allowing independent activation of smaller row segments. This segmentation enables the system to activate only the necessary portion of a row (e.g., 128 bits instead of 512 bits), reducing the energy required for row activation while maintaining high bandwidth through parallel sub-channel operations.
2Use of energy by moving object
If fine-grained row activation is implemented, then row energy consumption decreases, but device complexity increases
Solution Approach 1:
The DRAM bank is segmented into multiple sub-channels, each with its own row buffer and column address storage. This segmentation allows independent activation and operation of sub-channels, enabling fine-grained control over which portions of the DRAM are activated, thereby reducing energy consumption for partial row accesses.
Solution Approach 2:
The system dynamically selects and activates only the necessary sub-channels based on the access pattern requirements. The control logic can enable or disable specific sub-channels on-the-fly, providing dynamic energy management that adapts to workload characteristics without requiring static architectural changes.
3Productivity
If sub-channel architecture is used, then bandwidth utilization improves, but manufacturing complexity increases
Solution Approach 1:
The patent implements sub-channels by dividing the DRAM bank into separable units with distinct row buffers and column address storage. This modular segmentation allows for systematic fabrication processes where each sub-channel can be manufactured as a repeating unit, simplifying the overall manufacturing complexity despite the increased architectural functionality.
Data Source
AI summary
A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.