DRAM Sub-array Refresh Controller with Open Page Detection
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Solution Overview
Problem
The increased refresh rate of dynamic random access memory (DRAM) due to higher density and smaller feature sizes leads to performance impediments and power consumption issues, as all DRAM banks are typically closed during refresh operations, restricting access and causing potential yield loss from weak retention cells.
Innovation Solution
The method involves detecting open pages within DRAM sub-arrays and delaying refresh commands to target rows within these open sub-arrays, allowing other sub-arrays to remain open and accessible during refresh operations, thereby enabling sub-array level parallelism and reducing the need for full bank closure during refresh.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM refresh rate is increased to compensate for larger number of leaking memory cells in higher density arrays, then retention reliability is improved, but system performance deteriorates due to bank closure requirements
Solution Approach 1:
The patent divides a DRAM bank into multiple sub-arrays, allowing independent refresh operations on individual sub-arrays while other sub-arrays remain accessible. This segmentation enables parallel operations where refresh commands can be issued to one sub-array without closing the entire bank, thus maintaining retention reliability while preserving system performance through continued access to non-refreshed sub-arrays.
2Reliability
If all open pages of a memory bank are closed before refresh, then refresh operation can be completed, but access time increases and system performance is impeded
Solution Approach 1:
By segmenting the bank into sub-arrays, the patent allows refresh operations to be performed on specific sub-arrays without requiring closure of the entire bank. Open pages in other sub-arrays can remain accessible during refresh, eliminating the need to close all pages before refresh and thereby reducing access time losses.
Solution Approach 2:
The patent tracks open page status across sub-arrays using CBR counters and control logic before issuing refresh commands. This preliminary detection allows the system to identify which sub-arrays have open pages and delay refresh commands only for those specific sub-arrays, while proceeding with refresh on sub-arrays without open pages, thus minimizing access time penalties.
3Reliability
If DRAM bank access is not allowed during refresh operation, then refresh integrity is maintained, but productivity decreases due to access restrictions
Solution Approach 1:
The patent enables simultaneous access to sub-arrays that are not currently being refreshed while refresh operations proceed on other sub-arrays. This segmentation breaks the all-or-nothing access restriction, allowing productivity to be maintained through parallel access to non-refreshed sub-arrays while refresh integrity is preserved on the active sub-array.
Solution Approach 2:
By allowing access to continue on non-refreshed sub-arrays during refresh operations on other sub-arrays, the patent maintains continuous useful action throughout the bank. System productivity is improved because memory access operations can proceed without interruption on available sub-arrays, eliminating the complete access halt that would otherwise occur during refresh.
4Productivity
If sub-array level parallelism is enabled during refresh, then system performance is improved, but control complexity increases
Solution Approach 1:
The patent introduces CBR (Column Before Row) counters and control logic at the sub-array level to track open page status independently for each sub-array. This segmented tracking approach enables sophisticated parallel refresh control without requiring complex global coordination, as each sub-array can be managed independently based on its own CBR counter state, thus achieving performance improvement with manageable control complexity.
Data Source
AI summary
A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.