DRAM Timing Adjuster Allocation for Refresh Area Reduction

Multiple timing adjustment circuits are merged into a single shared circuit. The patent implements a common timing adjustment circuit that serves multiple memory banks simultaneously, eliminating the need for separate timing adjustment circuits in each bank. This merging approach maintains the timing adjustment functionality while significantly reducing the total chip area occupied by these circuits.

A single timing adjustment circuit is designed to perform multiple functions for different memory banks. The circuit can dynamically adjust timing parameters for various memory banks based on their specific refresh requirements, making one circuit universal enough to replace multiple dedicated circuits. This multi-functionality is achieved through configurable control logic that adapts the circuit behavior to different bank needs.

The patent implements dynamic allocation of timing adjusters based on real-time refresh operation requirements. Instead of having fixed dedicated adjusters for each memory bank, the system dynamically assigns available adjusters to different banks as needed. This dynamic approach allows a reduced number of physical adjusters to handle concurrent refresh operations by time-multiplexing their usage across different banks, maintaining productivity while minimizing chip area.

A center circuit acts as an intermediary between memory banks and timing adjusters. This center circuit coordinates and manages the allocation of a limited number of timing adjusters to multiple memory banks performing concurrent refresh operations. The center circuit ensures proper timing and coordination, allowing efficient utilization of fewer adjusters across multiple banks without compromising the concurrent operation capability.