DRAM Timing Verification for Illegal Command Detection
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Solution Overview
Problem
Memory devices face issues with executing illegal commands that violate array timings, leading to potential data corruption or loss, particularly in high-security applications like autonomous vehicles, where errors are not tolerable.
Innovation Solution
Incorporating a detection component within the memory device that uses timers and counters to check if array timings relevant to a received command have elapsed, preventing the execution of illegal commands and ensuring data integrity by refraining from executing such commands and reporting errors to the host device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device executes all received commands without verification, then the productivity is improved, but the reliability deteriorates due to potential data corruption from illegal commands
Solution Approach 1:
The patent implements preliminary verification of commands by checking array timings before execution. The detection component examines whether required timing intervals have elapsed since previous operations on the same array locations, and only permits command execution if timing requirements are satisfied. This advance checking prevents illegal commands from causing data corruption while maintaining efficient processing of valid commands.
2Reliability
If the memory device implements timing verification for all commands, then the reliability is improved, but the device complexity increases due to additional detection components
Solution Approach 1:
The patent integrates the detection component into the existing memory device architecture, allowing it to perform multiple functions: verifying timing requirements for various command types (read, write, refresh), tracking multiple array locations, and coordinating with the memory controller. This multi-functional design achieves comprehensive reliability improvement without proportionally increasing device complexity.
Solution Approach 2:
The memory device performs self-verification of timing requirements through its internal detection component, which autonomously monitors array timing states and determines whether commands are legal to execute. This self-service approach eliminates the need for external verification hardware, thereby improving reliability while minimizing increases in overall system complexity.
3Reliability
If the memory device checks timing requirements for every command, then the reliability is improved, but the loss of time increases due to verification overhead
Solution Approach 1:
The detection component continuously monitors and pre-calculates timing requirement status in the background, maintaining up-to-date information about when array locations will be available for new operations. When a command arrives, the verification process simply checks pre-computed timing data rather than performing full timing calculations, significantly reducing verification time while maintaining reliable command validation.
Data Source
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AI summary
Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.