DRAM Timing Synchronization via Slowest Chip Reference
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Solution Overview
Problem
In semiconductor devices with multiple core chips and an interface chip, variations in manufacturing process conditions lead to differences in operation speed among core chips, resulting in reduced latch margin and potential inaccuracies in data read operations, necessitating multiple latch timing control circuits on the interface chip, which is inefficient and wasteful.
Innovation Solution
A method is implemented where the output timing adjustment circuit in each core chip and the input timing adjustment circuit in the interface chip are set to the longest time, ensuring a common latch margin for read data, eliminating the need for multiple latch timing control circuits and allowing accurate data capture by synchronizing with the slowest core chip's timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch timing control circuits are implemented on the interface chip to accommodate speed variations among core chips, then data capture accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the latch timing control functionality from multiple separate circuits into a single shared control circuit. This is achieved by introducing a reference clock signal that is distributed to all core chips, allowing the interface chip to use one latch timing control circuit to synchronize data capture from multiple core chips with different operation speeds, thereby reducing device complexity while maintaining data capture accuracy
Solution Approach 2:
The single latch timing control circuit on the interface chip is designed to universally handle timing synchronization for data from all core chips. By using a common reference clock and adjustable delay mechanisms, this single circuit performs the function that would otherwise require multiple dedicated circuits, achieving multi-functionality and reducing overall system complexity
2Device complexity
If the interface chip uses a single latch timing control circuit for all core chips, then device complexity is reduced, but latch margin becomes insufficient for fast core chips
Solution Approach 1:
The patent implements dynamic timing adjustment mechanisms that allow the latch timing control circuit to adapt its timing parameters based on the operation speed of each core chip. By introducing adjustable delay circuits and reference clock distributions, the system dynamically optimizes the latch timing for each core chip, ensuring sufficient latch margin for fast core chips while maintaining compatibility with slower ones
Solution Approach 2:
The system changes the timing parameters of the latch control circuit dynamically. By adjusting the phase and delay of the reference clock signal distributed to different core chips, the system optimizes the latch margin for each chip's operation speed. This parameter adjustment allows a single control circuit to handle varying timing requirements without compromising reliability
3Manufacturing precision
If each core chip operates at its own optimal speed determined by manufacturing process conditions, then manufacturing precision is maintained, but synchronization of data output timing becomes difficult
Solution Approach 1:
The patent creates a common timing reference level by distributing a standardized reference clock signal to all core chips. This equipotential approach allows each core chip to operate independently at its manufacturing-determined speed while still being synchronized to a common timing baseline, simplifying the synchronization mechanism without compromising manufacturing precision
Solution Approach 2:
The reference clock signal acts as an intermediary between the interface chip and multiple core chips. This intermediary timing signal mediates the synchronization between core chips with different operation speeds, allowing each to maintain its manufacturing-optimized speed while achieving coordinated data output timing through the common reference
Data Source
AI summary
A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.