DRAM Trench Capacitor Isolation Using Shallow Trench Isolation
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Solution Overview
Problem
The challenge in scaling down dynamic random access memory (DRAM) cells is the difficulty in maintaining sufficient electrical isolation between access transistors and trench capacitors, particularly due to the limitations of thick collar oxides and buried insulator formation in bulk substrates, which are costly and complex to process.
Innovation Solution
A semiconductor structure is formed with semiconductor fins and trench capacitors, where a shallow trench isolation layer provides electrical isolation, and a strap structure is created by filling via cavities with conductive material to connect the source region of the access transistor to the trench capacitor, eliminating the need for thick collar oxides and complex buried insulator formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick collar oxide is used to provide electrical isolation in bulk substrate DRAM, then sufficient electrical isolation between access transistors and buried plate is achieved, but the trench capacitor dimensions become too small to support the thick collar while leaving room for conformal fill of the inner electrode
Solution Approach 1:
The patent extracts the electrical isolation function from the traditional collar oxide structure and relocates it to a shallow trench isolation layer formed between the semiconductor fins. This separates the isolation function from the capacitor structure, allowing the collar oxide to be removed while maintaining electrical isolation through the shallow trench isolation layer that laterally surrounds the trench capacitor.
Solution Approach 2:
The patent transitions from a vertical isolation approach (thick collar oxide at the top of the trench) to a lateral isolation approach (shallow trench isolation layer between fins). By moving the isolation structure to another spatial dimension, the design achieves electrical isolation without compromising the conformal fill capability of the inner electrode.
2Reliability
If semiconductor-on-oxide (SOI) substrate is used to provide electrical isolation, then sufficient isolation between access transistors and buried plate is achieved, but the substrate cost increases significantly
Solution Approach 1:
The patent replaces the expensive SOI substrate with a bulk substrate combined with a disposable shallow trench isolation layer. The shallow trench isolation layer provides the necessary electrical isolation function at a fraction of the cost of SOI substrates, using standard bulk substrate materials and conventional isolation techniques.
Solution Approach 2:
The patent introduces a shallow trench isolation layer as an intermediary structure between the bulk substrate and the trench capacitor. This intermediate layer provides the electrical isolation function that would otherwise require expensive SOI substrates, acting as a mediator that enables cost-effective isolation in bulk substrate DRAM.
3Reliability
If complex processing steps are used to form a buried insulator layer in bulk substrate, then electrical isolation is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent makes the shallow trench isolation layer multi-functional: it provides electrical isolation between the access transistor and buried plate, serves as a structural support for the trench capacitor, and enables subsequent processing steps. This universal structure eliminates the need for separate buried insulator formation steps.
Solution Approach 2:
The patent merges the electrical isolation function with the existing shallow trench isolation structure used in standard CMOS processing. By combining the isolation requirement with a structure already present in the manufacturing process, the patent eliminates complex additional steps for buried insulator formation.
Data Source
AI summary
After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.