DRAM Victim Row Refresh via Access Counting to Thwart Row-Hammer Attacks
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Solution Overview
Problem
Row-hammer attacks in DRAM devices cause unintended bit flips in adjacent memory cells due to frequent access, compromising data integrity and security.
Innovation Solution
A memory controller with a row-hammer victim page address cache (RVPAC) that increments a count value for victim rows and issues a command to re-energize them when the count reaches a threshold, effectively thwarting the attack by restoring voltage levels before significant bit flips occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent access to target rows is performed to execute operations, then operational productivity is improved, but voltage accumulation in adjacent victim rows causes bit flips and data corruption
Solution Approach 1:
The patent applies preliminary action by proactively refreshing victim rows before bit flips can occur. The system monitors access patterns to target rows and preemptively issues refresh commands to adjacent victim rows based on predicted vulnerability, preventing data corruption before it happens rather than reacting after bit flips occur
Solution Approach 2:
The patent implements feedback mechanisms by tracking access patterns to target rows and using this information to determine when victim rows need refreshing. The system continuously monitors row access frequency and voltage degradation patterns, adjusting refresh timing based on real-time conditions to prevent bit flips while optimizing performance
2Reliability
If periodic refresh of all DRAM rows is performed to restore voltage levels, then data integrity is maintained, but operational time is lost due to refresh cycles
Solution Approach 1:
The patent applies local quality by selectively refreshing only the specific victim rows that are vulnerable to row-hammer attacks rather than performing blanket refreshes of all DRAM rows. The system identifies and targets only those adjacent rows that have experienced voltage degradation from nearby target row accesses, leaving other rows undisturbed and maintaining their normal operation
Solution Approach 2:
The patent implements periodic action through targeted refresh operations that occur at specific intervals based on monitored access patterns. Instead of continuous or fixed-period refreshes of all rows, the system schedules refresh commands for victim rows based on the periodic accumulation of voltage degradation from target row accesses, optimizing the timing to prevent bit flips while minimizing disruption
3Object-affected harmful factors
If monitoring and prevention mechanisms are added to detect row-hammer attacks, then security is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the memory controller to perform multiple functions: it simultaneously manages normal read/write operations, monitors access patterns for row-hammer detection, tracks voltage degradation in victim rows, and executes targeted refresh operations. This multi-functional approach consolidates security and reliability features within the existing controller infrastructure rather than adding separate dedicated systems
Solution Approach 2:
The patent implements self-service by enabling the memory controller to autonomously detect vulnerable victim rows and execute refresh operations without external intervention. The system automatically monitors its own operational state, identifies rows at risk from row-hammer attacks, and performs corrective refresh actions independently, reducing the need for additional external monitoring hardware or complex coordination protocols
Data Source
AI summary
A memory controller for a (DRAM) memory processes an (access) command for a target row in the memory, increments a count value for each victim row associated with the target row, and issues a (dummy activate) command for a victim row whose count value reaches a specified threshold. By tracking victim rows instead of target rows, the memory controller can thwart both single-sided and double-sided row-hammer attacks. The memory controller maintains the victim-row addresses and corresponding command counts in a TCAM memory to detect rows that may be prone to row-hammer attacks. If so, then the memory controller issues dummy activate commands to the corresponding memory rows to thwart such row-hammer attacks.