DRAM Cell Voltage Boosting via Sense Amplifier Bus Shorting
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Solution Overview
Problem
In dynamic random access memory (DRAM) devices, particularly in SDRAM, the wordline shutting off before full cell voltage is restored can lead to data loss, especially for memory cells close to the wordline driver circuit, resulting in reduced data signal integrity during write operations.
Innovation Solution
The proposed solution involves modifying the global wordline drivers to boost the sense amplifier power supply bus voltage by shorting the row driver signal/bus to the ACT voltage, allowing the cell voltage to reach a higher level before wordline shutdown, thereby improving data signal retention without adding additional power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the wordline is shut off to complete the write operation, then the write speed is improved, but the cell voltage cannot be fully restored leading to data loss
Solution Approach 1:
The patent applies preliminary action by restoring the cell voltage to a sufficient level before the wordline is shut off. The write operation is initiated, and during the write recovery time period, the cell voltage is allowed to restore partially or fully before the wordline shutdown occurs. This ensures that when the wordline is eventually shut off to complete the write operation quickly, the cell voltage has already reached a safe level that prevents data loss, thus resolving the contradiction between write speed and data integrity.
2Reliability
If additional power supplies are added to boost cell voltage, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by utilizing existing system resources to achieve voltage boosting without adding dedicated new components. The sense amplifier power supply bus is used to provide the boosted voltage to the memory cell, and the row driver signal bus is utilized for voltage sharing. These existing structures serve the additional function of voltage boosting during write operations, thereby improving data retention while avoiding increased device complexity from additional power supplies.
Data Source
AI summary
A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.