DRAM Power Reduction via Dynamic Voltage Regulation
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Solution Overview
Problem
As electronic and computing devices demand larger storage capacities and increased functionality, dynamic random access memories (DRAMs) face challenges in reducing power consumption due to parasitic effects and leakage currents, which require regular refreshing and consume more power during standby periods.
Innovation Solution
Implementing a system with an active mode and a self-refresh mode, where a memory device operates at a lower voltage level during self-refresh mode, reducing power consumption by using a voltage regulator to supply a first voltage level during active operations and a second, lower voltage level during self-refresh mode, as provided by registers, thereby improving overall power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAMs perform regular refreshing operations to combat parasitic effects and leakage currents, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the voltage level adjustable based on operational mode. The system transitions from a static voltage supply to a dynamic voltage regulation mechanism that adapts to different states (active vs. self-refresh mode), allowing the memory device to optimize power consumption while maintaining data retention through periodic refreshing operations.
Solution Approach 2:
The patent implements parameter changes by varying the voltage level supplied to the memory device depending on the operational mode. During self-refresh mode, a lower voltage level is provided compared to active mode, enabling the system to reduce power consumption during refreshing operations while still maintaining sufficient voltage for data retention.
2Use of energy by moving object
If DRAMs operate in self-refresh mode during standby periods, then power consumption is reduced, but the complexity of voltage control increases
Solution Approach 1:
The patent applies self-service by enabling the memory device to automatically manage its own voltage levels and refresh operations without requiring external intervention. The self-refresh mode allows the device to autonomously perform voltage regulation and data retention operations, reducing the need for complex external voltage control mechanisms.
Solution Approach 2:
The system uses dynamics in voltage control by implementing a voltage regulator that automatically adjusts the supplied voltage based on the operational mode detected by the memory device. This dynamic adaptation simplifies the overall control architecture compared to static voltage regulation systems.
3Use of energy by moving object
If a lower voltage level is supplied during self-refresh mode, then power consumption is reduced, but the challenge of maintaining adequate voltage for data retention increases
Solution Approach 1:
The patent applies parameter changes by carefully selecting and optimizing the lower voltage level supplied during self-refresh mode. The voltage regulator provides a reduced voltage compared to active mode while ensuring it remains sufficient to maintain data retention during the refresh operation, achieving a balance between power savings and reliability.
Solution Approach 2:
The system implements feedback mechanisms where the memory device monitors its operational state and provides information to the voltage regulator about the required voltage levels. This feedback ensures that the lower voltage supplied during self-refresh mode is adequate for maintaining data retention, dynamically adjusting the voltage based on actual device needs.
Data Source
AI summary
Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.