DRAM Weakness Detector Segments Memory Areas for Adaptive Refresh
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Solution Overview
Problem
Conventional DRAMs perform refresh operations based on average cell data retention time, leading to unnecessary power consumption and fixed refresh periods, which do not adapt to varying data retention characteristics of cells, resulting in inefficient data maintenance and potential data failures.
Innovation Solution
A semiconductor device with a scrubbing circuit, weakness detector, and refresh controller that divides the memory device into areas based on error occurrence, adjusts refresh periods, and generates specific refresh requests and commands to optimize refresh operations, reducing unnecessary refreshes and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed based on average cell data retention time, then data stability is maintained, but power consumption increases due to unnecessary frequent refreshes
Solution Approach 1:
The memory device is divided into multiple areas based on error occurrence information, with each area having its own independent refresh period. This segmentation allows marginal cells to receive more frequent refreshes while average cells are refreshed less frequently, reducing overall power consumption while maintaining data stability.
Solution Approach 2:
Different refresh periods are applied to different areas of the memory device based on their specific data retention characteristics. Areas with marginal cells (higher error occurrence) receive shorter refresh periods, while areas with average cells receive longer refresh periods, optimizing the balance between reliability and power consumption.
2Device complexity
If a fixed refresh period is used during memory device operation, then control is simplified, but data failures cannot be avoided when cell data retention characteristics deteriorate
Solution Approach 1:
The refresh period is changed from a fixed value to a dynamically adjustable parameter. The refresh controller automatically adjusts the refresh period for each area based on real-time error occurrence information, allowing the system to adapt to deteriorating cell characteristics without increasing operational complexity.
Solution Approach 2:
The system uses error occurrence information as feedback to continuously optimize refresh periods. The weakness detector monitors errors and provides information to the refresh controller, which adjusts refresh periods accordingly, creating a closed-loop system that improves reliability while maintaining simple control through automated feedback mechanisms.
3Reliability
If auto-refresh commands are frequently issued to maintain data stability, then data retention is improved, but command bus utilization decreases and data bus efficiency is reduced
Solution Approach 1:
The memory device is segmented into multiple areas with different refresh requirements. By issuing refresh commands selectively to specific areas rather than universally, the system reduces the frequency of auto-refresh commands on the command bus and minimizes conflicts with data bus operations, improving overall system productivity while maintaining data retention.
Data Source
AI summary
In an embodiment a semiconductor device may include a weakness detector configured to manage error occurrence information by dividing the memory device into a plurality of areas, to control a first refresh period for a first refresh request at each of the plurality of areas based on the error occurrence information and to generate a second refresh request for a second refresh address included in each of the plurality of areas based on the error occurrence information, and a refresh controller configured to generate a first refresh command according to the first refresh period and output the first refresh command to the memory device and to output a second refresh command and the second refresh address to the memory device according to the second refresh request and the second refresh address.