Dragonfly Processor Interconnect Network Scalability
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Solution Overview
Problem
Processor interconnect networks in multiprocessor systems face challenges in achieving efficient communication between processing nodes while controlling the number of links and cost, especially with high-speed fiber optic links, due to impractical direct linking of nodes and high costs associated with long connections.
Innovation Solution
The dragonfly topology network uses high-radix routers grouped into subnetworks as virtual routers, reducing the number of global channels per packet to one, and employs selective virtual channel discrimination and credit round-trip latency to balance load and sense congestion, optimizing routing decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct linking of each node to each other node is implemented, then communication speed between processors is improved, but the number of connections becomes impractically large
Solution Approach 1:
The network is segmented into multiple groups of routers, where each group contains multiple routers. This segmentation allows the network to scale by dividing the connectivity requirement into manageable chunks, reducing the number of direct connections needed while maintaining communication efficiency.
Solution Approach 2:
Routers within each group act as intermediaries that aggregate connections from multiple processing nodes. Instead of direct node-to-node linking, traffic is routed through these intermediary routers, which reduce the overall connection count while preserving communication capabilities.
2Speed
If long connections or high-speed fiber optic links are used, then communication performance is improved, but cost increases significantly
Solution Approach 1:
The patent implements local quality by using high-speed fiber optic links only where necessary (for long-distance group interconnections) while using lower-cost connections for shorter distances within groups. This differentiated approach optimizes performance where needed while controlling costs in less critical paths.
Solution Approach 2:
The network introduces a hierarchical dimension with multiple levels: intra-group connections and inter-group connections. This dimensional organization allows traffic to be routed through optimal paths at each level, reducing the need for expensive long-haul connections and enabling cost-effective network design.
3Productivity
If the number of processors increases to thousands, then processing power is improved, but direct linking becomes impossible
Solution Approach 1:
The network segments processors into multiple groups, each managed by a subset of routers. This segmentation enables the system to scale to thousands of processors by organizing them into manageable groups, avoiding the impossibility of direct linking while maintaining scalability.
Solution Approach 2:
The patent adds hierarchical dimensions to the network topology, creating multi-level routing paths. This dimensional approach enables thousands of processors to be connected through intermediate routing levels, making the system scalable beyond what flat direct-linking architectures can achieve.
4Adaptability or versatility
If more intermediate nodes are added between sending and receiving processing nodes, then routing flexibility is improved, but latency increases
Solution Approach 1:
The patent implements dynamic routing capabilities where the network can adaptively select paths based on current traffic conditions. This dynamic behavior allows the system to maintain low latency by choosing optimal routes while preserving routing flexibility, as the path selection can change in response to network state.
Solution Approach 2:
The network performs preliminary routing decisions at the group level before packets are forwarded to destination groups. This preliminary action reduces latency by making early routing choices that minimize intermediate hops, while still maintaining flexibility for final destination-specific routing within groups.
Data Source
AI summary
A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.


