DRAM Air Gap Structure Reduces Parasitic Capacitance
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges with parasitic capacitance between bit lines and capacitive contact structures, which affects performance and yield, particularly as devices scale down, and reducing this capacitance through conventional methods either increases resistance or requires larger chip areas.
Innovation Solution
Incorporating a buried word line and bit line structures with an air gap structure surrounding the capacitive contact structures, where the air gaps expose shallow trench isolation and substrate surfaces, reducing parasitic capacitance and resistance while maintaining performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the height of the bit line is decreased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the resistance of the bit line increases
Solution Approach 1:
An air gap structure is introduced as an intermediary between the bit line and the capacitive contact structure. This air gap acts as a mediator that reduces the parasitic capacitance coupling between these two structures without requiring changes to the bit line dimensions that would increase resistance. The air gap provides electrical isolation while maintaining structural integrity.
Solution Approach 2:
The harmful dielectric material between the bit line and capacitive contact structure is removed and replaced with air. By extracting the solid dielectric and replacing it with air (which has lower permittivity), the parasitic capacitance is reduced without affecting the bit line's conductive properties.
2Object-affected harmful factors
If the length of the bit line is shortened to reduce parasitic capacitance, then the parasitic capacitance is decreased, but the chip area becomes larger
Solution Approach 1:
The air gap structure serves as an intermediary that reduces parasitic capacitance without requiring bit line shortening. This allows the bit line to maintain its full length for optimal signal transmission while still achieving capacitance reduction through the air gap mediation between the bit line and capacitive contact structure.
Solution Approach 2:
Instead of reducing parasitic capacitance by shortening the bit line in one dimension (length), the invention introduces a vertical dimension element - the air gap - between the bit line and capacitive contact structure. This dimensional approach allows capacitance reduction without compromising the bit line length or increasing chip area.
3Productivity
If devices are scaled down to improve integration, then the distance between bit line and capacitive contact structure becomes smaller, but parasitic capacitance problems become more serious
Solution Approach 1:
The air gap structure is introduced as a scaling-independent solution. As devices are scaled down and the distance between bit line and capacitive contact structure naturally decreases, the air gap maintains a consistent insulating effect that counteracts the increased capacitance coupling, allowing continued scaling without proportionally increasing parasitic capacitance issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap structure significantly decreases parasitic capacitance and resistance, enhancing writing rate and reliability of DRAM devices, allowing for improved performance and scalability without increasing chip area.
Implementation Method 1
Since air has a lower dielectric constant than a general dielectric material, the parasitic capacitance between the bit line and the capacitive contact structure may be significantly decreased
Data Source
AI summary
A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.