DRAM Contact Leakage Reduction via Local Doping

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Solution Overview

Problem

Integrated circuits, particularly DRAMs, face performance degradation due to leakage current in contact regions, which leads to charge loss and reduced data retention time, complicating the manufacturing process and requiring complex structures.

Innovation Solution

A method for manufacturing a low-leakage contact in MOS transistor devices involves forming a substrate with well structures, implanting impurities for threshold voltage adjustment, creating a gate stack, and forming lightly doped drain structures, spacers, and contact structures while using photo resist masks to prevent threshold voltage implantation in certain regions, thereby reducing leakage current and contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If threshold voltage implantation is performed to adjust transistor characteristics, then transistor performance is improved, but leakage current increases in contact regions

Engineering Contradiction:
Improvetransistor performanceVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different doping concentrations to different regions: the channel region receives threshold voltage implantation with higher dopant concentration to improve transistor performance, while the contact region maintains lower dopant concentration to minimize leakage current. This spatial differentiation of doping quality resolves the contradiction between performance enhancement and leakage reduction.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the doping process into distinct stages and regions. First, threshold voltage implantation is performed on the channel region, then contact region doping is performed separately with controlled concentration. This segmentation allows independent optimization of each region's electrical characteristics, achieving both improved transistor performance and reduced contact leakage.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If complex manufacturing processes are used to reduce leakage, then leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent employs self-aligned doping processes where previously formed structures (such as gate electrodes or isolation regions) automatically serve as masks for subsequent doping steps. This eliminates the need for additional complex masking processes, reducing manufacturing complexity while achieving precise spatial control over doping concentrations to minimize leakage current.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent controls leakage current by adjusting doping concentration parameters rather than adding complex structural elements. By optimizing the dopant concentration in the contact region to be lower than in the channel region, the patent achieves leakage reduction through parameter optimization alone, avoiding increased device or process complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method results in improved device yields, reduced leakage current, lower contact resistance, and extended data retention time, allowing for longer intervals between refresh operations in DRAM memory devices.

Implementation Method 1

implanting impurities for threshold voltage adjustment into the first region using the patterned photo resist as a mask

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

a gate dielectric layer is grown to overlie the surface region

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS8324666B2DRAM cell transistor device and method
Publication Date: 2012.12.04 SEMICON MFG INT (SHANGHAI) CORP
  • US8324666B2 patent drawing
  • US8324666B2 patent drawing
  • US8324666B2 patent drawing

AI summary

A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region.