Interleaved Drain Doping for High-Voltage ESD Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated chips (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses, which can lead to failure in HBM ESD class 2 and greater devices, as existing solutions do not provide sufficient ESD protection.

Innovation Solution

The IC incorporates a semiconductor device with a drain region comprising multiple first and second doped regions, where the first doped regions have a higher concentration of dopants than the second doped regions, and the second doped regions are disposed laterally between the first doped regions, resulting in a high resistance across the drain region that mitigates voltage spikes from ESD pulses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing ESD protection solutions are used, then the IC structure remains simple, but the ESD protection level is insufficient and cannot withstand HBM ESD class 2 and greater pulses

Engineering Contradiction:
ImproveESD protection levelVSAvoiddrain region structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The drain region is segmented into multiple first doped regions and second doped regions arranged in an interleaved pattern. This segmentation creates multiple ESD protection paths and increases the overall ESD withstand capability without requiring a completely separate protection structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doped regions are assigned different doping concentrations locally within the drain region. The first doped regions have a first doping concentration while the second doped regions have a second doping concentration, creating localized variations in electrical properties that enhance ESD protection at specific locations

Inventive Principle:
Principle #3Local quality

2Reliability

If the drain region uses uniform doping, then the device structure is simple to manufacture, but voltage spikes from ESD pulses are not effectively mitigated

Engineering Contradiction:
Improvevoltage spike mitigationVSAvoiddoping process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The doping process is segmented into multiple steps, with different doping concentrations applied to different regions. This allows effective voltage spike mitigation through controlled resistance distribution while using standard semiconductor manufacturing techniques

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The doping concentration parameter is changed across different regions of the drain region. By varying the doping concentration between first and second doped regions, the electrical resistance is optimized to mitigate voltage spikes from ESD pulses

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the second doped regions are removed, then the manufacturing process is simplified, but the ESD protection capability is reduced

Engineering Contradiction:
ImproveESD protectionVSAvoiddoped regions configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The drain region is divided into alternating first doped regions and second doped regions, creating multiple ESD protection pathways. This segmented structure provides superior ESD protection compared to uniform doping while maintaining a regular, manufacturable pattern

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first and second doped regions are merged into a single drain region structure that works together to provide ESD protection. The combination of regions with different doping concentrations creates an integrated protection mechanism

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration provides improved ESD protection, enabling the IC to withstand ESD pulses with voltages greater than or equal to 2,000 V, thus meeting or exceeding the specifications for certain applications.

Implementation Method 1

the second doped regions are disposed laterally between the first doped regions, resulting in a high resistance across the drain region that mitigates voltage spikes from ESD pulses

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12237323B2Semiconductor device having improved electrostatic discharge protection
Publication Date: 2025.02.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12237323B2 patent drawing
  • US12237323B2 patent drawing
  • US12237323B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.