Drain Electrode Overlap Design for Kickback Voltage Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As display devices increase in size and image quality, the smaller pixel size leads to fluctuations in storage capacitance and parasitic capacitance, causing variations in kickback voltage, which degrade display quality.
Innovation Solution
The design includes a drain electrode with specific overlap portions and non-overlap portions to stabilize the capacitance ratio between the parasitic capacitor, storage capacitor, and liquid crystal capacitor, maintaining a constant kickback voltage by adjusting the lengths and areas of these overlap regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If display device size increases and pixel size decreases to improve image quality, then display resolution and image quality are improved, but storage capacitance and parasitic capacitance fluctuate causing kickback voltage variation
Solution Approach 1:
The patent changes the geometric parameters of the drain electrode by introducing overlap portions and non-overlap portions. Specifically, the drain electrode is designed to overlap with both the gate electrode and the storage electrode at different regions, creating controlled capacitance relationships. This parameter change allows the capacitance ratio between parasitic capacitor and storage capacitor to be stabilized, thereby maintaining constant kickback voltage despite pixel size reduction
Solution Approach 2:
The drain electrode is segmented into functionally distinct regions: a first overlap portion overlapping the gate electrode, a second overlap portion overlapping the storage electrode, and non-overlap portions between them. This segmentation allows independent control of parasitic capacitance and storage capacitance contributions, enabling stabilization of their ratio and thus kickback voltage
2Productivity
If mask misalignment occurs during manufacturing, then production efficiency is maintained, but capacitance values fluctuate causing kickback voltage variation and degraded display quality
Solution Approach 1:
The patent introduces design flexibility through the drain electrode configuration that can dynamically adapt to alignment variations. The overlap portions are designed with specific length ratios (first overlap portion length of 3-5 μm and second overlap portion length of 20-40 μm) that provide a buffer zone, allowing the structure to maintain functional performance even when mask misalignment occurs during manufacturing
Solution Approach 2:
The non-overlap portions of the drain electrode act as cushioning regions that compensate for potential misalignment. By designing these non-overlap portions with appropriate dimensions, the patent creates a tolerance buffer that prevents complete overlap loss even when mask misalignment occurs, thereby maintaining stable capacitance ratios and kickback voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures consistent display quality by maintaining a constant kickback voltage, even with misalignment of the source and drain electrodes due to mask misalignment, thereby improving display performance.
Implementation Method 1
The capacitor includes a liquid crystal capacitor, which is a capacitance component of the liquid crystal, a storage capacitor which compensates for the charge storage capability of the liquid crystal capacitor, and a parasitic capacitor which is formed between a gate line and source and drain electrodes
Data Source
AI summary
A display device including: a first substrate; a gate line extending along a first direction on the first substrate; a data line disposed on the first substrate, insulated from the gate line, and extending along a second direction that intersects the first direction; a gate electrode protruding from the gate line; a source electrode extending from the data line; a drain electrode spaced apart from the source electrode; a pixel electrode electrically connected to the drain electrode; and a storage electrode spaced apart from the gate line and the gate electrode. The drain electrode includes a first overlap portion overlapping the gate electrode and a second overlap portion overlapping the storage electrode, and the second overlap portion overlaps at least a part of the pixel electrode.