Drain Extended Transistor Well Tap Reduces Voltage Gradient
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Solution Overview
Problem
Existing semiconductor circuits with mixed signal technology require dual gate oxide processes or cascoding of drain extended transistors to handle voltage differences between analog and digital circuits, leading to increased complexity and cost due to the need for different gate oxide thicknesses in p-channel and n-channel transistors.
Innovation Solution
A transistor design with a well tap region closer to the interface between semiconductor regions, allowing for a single gate oxide thickness across all transistors, which reduces the voltage gradient and eliminates the need for dual gate oxide processes by using a well tap conductor to manage voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual gate oxide process is used to handle voltage differences between analog and digital circuits, then transistor reliability under high voltage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies local quality by creating a drain extension region with different doping characteristics than the main channel region. The drain extension has a first doping concentration while the channel has a second doping concentration, allowing localized optimization of electrical properties in different regions of the transistor to handle voltage differences without requiring dual gate oxide processes
Solution Approach 2:
The patent changes the doping concentration parameter spatially within the semiconductor structure. By having the drain extension region with a first doping concentration and the channel region with a second doping concentration, the electrical characteristics are adjusted locally to manage voltage gradients and eliminate the need for dual gate oxide thicknesses
2Strength
If p-channel transistors use thick gate oxide to withstand high voltage, then breakdown protection is improved, but manufacturing precision requirements increase due to dual thickness processes
Solution Approach 1:
Instead of using thick gate oxide universally for breakdown protection, the patent applies local quality by modifying the doping concentration in the drain extension region. This localized doping adjustment provides the necessary electrical isolation and voltage handling capability without requiring increased gate oxide thickness, thereby maintaining uniform oxide dimensions across all transistors
Solution Approach 2:
The patent uses the same gate oxide thickness for both p-channel and n-channel transistors, copying the oxide layer parameters across different transistor types. This eliminates the need for separate thick oxide processes for p-channel devices while still achieving breakdown protection through the doped drain extension structure
3Adaptability or versatility
If cascode configuration of drain extended transistors is used for voltage level shifting, then voltage compatibility between analog and digital circuits is improved, but device complexity and area increase
Solution Approach 1:
The patent merges the voltage level shifting function into a single transistor structure by combining the drain extension region with the channel region in one device. This eliminates the need for separate cascode-configured transistors to achieve voltage compatibility, as the single transistor with differentiated doping regions can handle both voltage levels directly
Data Source
AI summary
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.