Drain-Gate Isolation for MOSFET Breakdown Voltage
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Solution Overview
Problem
Semiconductor devices with MOS transistors face limitations in achieving high breakdown voltage and electrostatic discharge (ESD) resistance, particularly when mounting different types of MOS transistors on the same substrate, as existing structures suffer from field concentration and gate oxide film breakdown.
Innovation Solution
A semiconductor device design featuring a drain-gate isolation portion between the drain region and the gate insulation film, which spaces the drain region and gate insulation film, reducing field concentration and allowing for a thinner gate insulation film without breakdown, while also enhancing ESD resistance by distributing surge current into the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate insulation film is made thinner to reduce ON-resistance, then the ON-resistance decreases, but the breakdown voltage decreases due to field concentration at the drain region
Solution Approach 1:
A drain-gate isolation portion is introduced as an intermediary structure between the drain region and the gate insulation film. This isolation portion prevents direct contact and reduces field concentration at the drain-gate interface, allowing the gate insulation film to be made thinner without causing breakdown. The isolation portion acts as a mediator that protects the gate insulation film from the high electric field while maintaining low ON-resistance.
2Adaptability or versatility
If different types of MOS transistors (DMOSFET and MOSFET) are mounted on the same substrate to achieve high breakdown voltage and low breakdown voltage devices, then the breakdown voltage range is extended, but the manufacturing process becomes significantly complicated
Solution Approach 1:
The drain-gate isolation structure is designed to be universally applicable to different types of MOS transistors. By using the same basic isolation technique for both high breakdown voltage devices and low breakdown voltage devices, the manufacturing process is simplified while still achieving the desired breakdown voltage range. The isolation portion can be integrated into various MOS transistor structures without requiring fundamentally different fabrication approaches.
3Device complexity
If the drain region and gate insulation film are in contact to simplify structure, then the device structure is simplified, but ESD resistance decreases due to surge current concentration
Solution Approach 1:
The drain-gate isolation portion serves as a protective intermediary that prevents direct contact between the drain region and gate insulation film. During electrostatic discharge events, this isolation structure prevents surge current from concentrating at the drain-gate interface, thereby protecting the gate insulation film from breakdown. The isolation portion maintains structural simplicity while significantly improving ESD resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves higher breakdown voltage and reduced ON-resistance, along with improved ESD resistance, and allows for easier mounting of various MOS transistors on the same substrate by simplifying the production process.
Implementation Method 1
field concentration (higher electric field) occurs in the vicinity of the drain region 104
Implementation Method 2
a surge current flows to be concentrated on an end portion of the gate oxide film 105 adjacent to the drain region 104, resulting in breakdown
Data Source
AI summary
An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.