DRAM Word Line With Segmented Upper and Lower Gates
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices face issues with gate induced drain leakage and sub-leakage, which are not adequately addressed by existing miniaturization efforts, necessitating a novel memory device structure to reduce these leaks.
Innovation Solution
The memory structure features two gates in a word line, with separate control over applied drain voltages, comprising an upper and lower gate with dielectric layers and liners, allowing independent gate voltage application to reduce both sub-leakage and gate induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drain voltage is increased to improve performance, then operation speed is improved, but the vertical electrical field increases causing increased gate induced drain leakage
Solution Approach 1:
The upper gate structure is segmented into multiple components (upper gate dielectric layer, upper gate liner, upper gate electrode) that work together to control the electrical field. This segmented structure allows independent optimization of the field control capability to suppress gate induced drain leakage while maintaining high drain voltage for fast operation.
Solution Approach 2:
The invention transitions from a single-plane gate to a three-dimensional upper-lower gate structure. This dimensional change enables independent control of vertical and lateral electrical fields, allowing high drain voltage for fast operation while the upper gate suppresses the vertical field component that causes gate induced drain leakage.
Data Source
AI summary
The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.