Drain Offset STI Insulating Film for High Voltage MOSFETs

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Solution Overview

Problem

The manufacture of high breakdown voltage MOSFETs using LOCOS type field insulating films for element isolation prolongs treatment steps and increases costs, while using STI type field insulating films leads to reliability issues due to high-energy electron generation and gate insulating film deterioration, particularly in high breakdown voltage P-type LDMOSFETs.

Innovation Solution

A method of manufacturing a semiconductor integrated circuit device involving the formation of a hard mask film, sidewall insulating films, and shallow trenches, followed by oxidation and filling with insulating films to create a drain offset STI insulating film, which improves reliability by reducing hot carrier generation and electric field concentration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If LOCOS type field insulating film is used for element isolation, then manufacturing cost is reduced and process complexity is simplified, but treatment time is prolonged and manufacturing productivity decreases

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidmanufacturing throughput
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent changes the isolation structure from LOCOS to a modified STI configuration with drain offset, adjusting geometric parameters (trench depth, offset dimensions) to simultaneously achieve simple processing and high productivity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The isolation structure is segmented into multiple components: shallow trench isolation and drain offset isolation, allowing independent optimization of each segment to resolve the contradiction between process simplicity and manufacturing efficiency

Inventive Principle:
Principle #1Segmentation

2Productivity

If STI type field insulating film is used for element isolation, then manufacturing time is reduced and productivity is improved, but high-energy electrons are generated causing gate insulating film deterioration and reliability decreases

Engineering Contradiction:
Improvemanufacturing throughputVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The drain offset isolation acts as an intermediary structure between the STI and the active region, mediating the electric field distribution to prevent high-energy electron generation while maintaining STI productivity benefits

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The drain offset isolation is positioned in advance to preemptively block the generation of high-energy electrons before they can reach the gate insulating film, preventing reliability degradation before it occurs

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If drain offset STI insulating film is formed with extended coverage, then reliability is improved by reducing hot carrier generation, but device area increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The drain offset isolation is applied locally only where needed near the drain region, providing reliability improvement through hot carrier suppression while limiting area increase to minimal necessary coverage

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method provides a high breakdown voltage MOSFET with improved reliability and reduced heat treatment time, effectively addressing the limitations of both LOCOS and STI isolation techniques.

Implementation Method 1

forming a sidewall insulating film on the side surface of the hard mask film of the first opening

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

oxidizing at least an exposed portion of the inner surface of the first shallow trench and the semiconductor region surface of the first main surface in the first opening

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 3

filling the first shallow trench and the first opening with an insulating film

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS9960075B2Method of manufacturing semiconductor integrated circuit device
Publication Date: 2018.05.01 RENESAS ELECTRONICS CORP
  • US9960075B2 patent drawing
  • US9960075B2 patent drawing
  • US9960075B2 patent drawing

AI summary

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.