Semiconductor Drain Pad Insulation for Oxidation-Resistant Marking
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Solution Overview
Problem
Semiconductor packages, particularly chip-scale packages, face challenges in reducing size and improving manufacturing efficiency while maintaining electrical connectivity and product marking durability, especially with exposed copper pads that are prone to oxidation and obscured markings.
Innovation Solution
A semiconductor device design featuring a semiconductor die with a common drain pad covered by an electrically insulating layer, allowing for independent switching of transistor devices and providing a stable surface for product marking, combined with a pad finishing layer for adhesion and protection, and a method of singulating wafers to produce devices with enhanced insulation and marking capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain pad is left exposed on the rear side of the semiconductor die, then electrical connectivity to the drain is achieved, but the copper pad is prone to oxidation and product markings become obscured
Solution Approach 1:
The patent applies different properties to different regions of the drain pad: the central region is covered by an electrically insulating layer for oxidation protection and marking stability, while the peripheral region remains exposed for electrical connectivity. This local differentiation resolves the contradiction between protection and connectivity.
Solution Approach 2:
The patent introduces an electrically insulating layer as an intermediary substance between the copper drain pad and the external environment. This layer provides oxidation protection and marking stability while the peripheral exposure maintains electrical connectivity, thus mediating between protection and connectivity requirements.
2Duration of action of stationary object
If the central portion of the drain pad is covered by an electrically insulating layer, then oxidation resistance and marking durability are improved, but electrical access to the drain is eliminated
Solution Approach 1:
The electrically insulating layer is selectively applied only to the central portion of the drain pad, leaving the peripheral region exposed. This local application ensures marking durability in the central area while maintaining electrical access through the peripheral area, thus resolving the contradiction.
3Productivity
If chip-scale packages are fabricated with exposed copper pads, then manufacturing efficiency is improved, but the pads are prone to oxidation and markings become obscured
Solution Approach 1:
The electrically insulating layer is applied selectively to the central portion of the drain pad in a controlled manufacturing process. This approach provides oxidation protection and marking stability without requiring complete pad coverage, thus maintaining manufacturing efficiency while improving reliability.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
In an embodiment, a semiconductor device 10 is provided that comprises a semiconductor die 11 comprising a front side 12, a rear side 13 opposing the front side 12 and side faces 14, a first transistor device 15 comprising a first source pad 16 and a first gate pad 17 on the front side 12, and a second transistor device 18 comprising a second source pad 19 and a second gate pad 20 on the front side. The first and second transistor devices 15, 18 each have a drain 20, 21 that is electrically coupled to a common drain pad 23 on the rear side 13 of the semiconductor die 11. The drain pad 23 has an upper surface 24 and side faces 25 and at least a central portion of the upper surface 24 is covered by a first electrically insulating layer 27.