Power Amplifier Equalization Using Drain-Power Bias Control
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Solution Overview
Problem
Existing power amplifiers face challenges in achieving good amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) metrics while maintaining high power added efficiency (PAE) and error vector magnitude (EVM) performance, often requiring complex digital pre-distortion and feedback loops that introduce design and performance issues.
Innovation Solution
The solution involves a novel equalization approach that controls bias conditions, such as bias voltage, to alter AM-AM and AM-PM profiles in power amplifiers, using cross-coupled common-gate transistors to generate equalization voltages that improve the 1 dB compression point and PAE, and a linearization method that pre-processes input signals to compensate for AM-PM variations using a reflective hybrid coupler and non-linear termination circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If digital pre-distortion with feedback loop is used to improve linearity and EVM performance, then AM-AM and AM-PM metrics are improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex feedback loop and digital pre-distortion circuitry from the amplifier system. Instead of using DPD with feedback, the invention employs a feedforward equalization circuit that directly compensates for AM-AM and AM-PM distortions without requiring signal sampling, processing, or feedback transmission, thereby resolving the contradiction between linearity improvement and complexity reduction
Solution Approach 2:
The patent introduces an equalization circuit as an intermediary component between the input signal and the power amplifier. This equalization circuit generates compensating signals that pre-correct the input signal to counteract the amplifier's non-linearities, achieving improved linearity and EVM performance without the need for complex feedback-based DPD circuitry
2Manufacturing precision
If operation point is moved further away from 1 dB compression point to improve linearity and EVM, then AM-AM and AM-PM metrics are improved, but power added efficiency deteriorates
Solution Approach 1:
The patent dynamically changes the bias conditions of the power amplifier based on the input signal power level. The equalization circuit adjusts bias voltages in real-time to optimize the amplifier's operating point, allowing the system to maintain good linearity and EVM performance while operating closer to the 1 dB compression point for improved power added efficiency, thus resolving the contradiction between linearity and efficiency
3Manufacturing precision
If bias voltage is increased to improve AM-AM and AM-PM metrics, then linearity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic bias control where the bias voltage applied to the power amplifier is continuously adjusted based on the instantaneous input signal power level. The equalization circuit modifies bias conditions in real-time, allowing the system to achieve improved AM-AM and AM-PM metrics only when needed (at high signal levels) while consuming less power during low-signal operation, thereby resolving the contradiction between linearity improvement and power consumption
Data Source
AI summary
Circuits and methods for achieving good AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance in an amplifier. Embodiments provide an equalization approach which compensates for AM-AM and AM-PM variations in an amplifier by controlling bias voltage versus output power to alter the AM-AM and AM-PM profiles imposed by the amplifier. Differential amplifier embodiments include cross-coupled common-gate transistors that generate an equalization voltage that alters the gate bias voltage of respective main FETs in proportion to a power level present at the respective drains of the main FETs. Single-ended amplifier embodiments include an equalization circuit that alters the bias voltage to the gate of a main FET in proportion to a power level present at the main FET drain. Embodiments may also include a linearization circuit which alters the AM-PM profile of an input signal to compensate for the AM-PM profile imposed by a coupled amplifier.