Drain-Programmed ROM Decoding for Higher Density and Lower Leakage
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Solution Overview
Problem
Existing mask-programmable read-only memories (ROMs) face challenges in achieving high density and reducing leakage currents due to layout constraints that force them into source programming implementations, which limit the number of bits stored per transistor.
Innovation Solution
Implementing a drain-programmed ROM architecture where the drain connection to transistors is mask programmed, allowing each transistor to encode multiple bits by selectively coupling it to bit lines or grounding, thereby reducing leakage currents and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source-programmed implementation is used to achieve high density, then storage density is improved, but leakage current increases due to gate-induced drain leakage
Solution Approach 1:
The patent inverts the traditional programming approach by programming the drain connection instead of the source connection. In conventional source-programmed ROMs, the source is connected to ground or floating, but this patent connects the drain to ground or floating states instead. This inversion eliminates gate-induced drain leakage because the drain is the terminal being controlled, not the source, thereby resolving the contradiction between achieving high density and reducing leakage current.
Solution Approach 2:
The patent changes the programming parameter from source connection state to drain connection state. By masking the drain to ground or leaving it floating during manufacturing, the transistor encoding is fundamentally altered. This parameter change allows the same physical structure to achieve both high density (through efficient encoding) and low leakage (by controlling the drain terminal directly), resolving the technical contradiction.
2Ease of manufacture
If source-programmed implementation is used, then layout constraints are satisfied, but the number of bits stored per transistor is limited
Solution Approach 1:
The patent makes each transistor serve multiple encoding functions by utilizing the drain connection state. Instead of each transistor storing only one bit through source programming, the drain-programmed approach allows each transistor to contribute to multiple bit positions through its drain connection state (grounded or floating). This multi-functionality increases the number of bits stored per transistor while maintaining layout compatibility, resolving the contradiction between ease of manufacture and storage capacity.
3Quantity of substance
If drain programming is implemented to increase density, then storage capacity is improved, but decoding complexity increases
Solution Approach 1:
The patent segments the decoding process into distinct phases: precharging phase, sensing phase, and decoding phase. During precharging, bit lines are prepared; during sensing, the actual transistor states are detected; during decoding, the sensed values are interpreted. This segmentation of the decoding process manages complexity by breaking it into manageable, sequential steps, allowing high storage capacity to be achieved without overwhelming decoding complexity.
Solution Approach 2:
The patent performs preliminary precharging of bit lines before the actual sensing operation. This preliminary action prepares the bit lines in a known state, simplifying the subsequent sensing and decoding operations. By precharging the bit lines to a standard voltage level before reading transistor states, the decoding complexity is reduced because the decoder only needs to detect deviations from the precharged state rather than interpreting absolute voltage levels, thus managing complexity while maintaining high storage capacity.
Data Source
AI summary
A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.