Drain-Select Isolation Structure With Low-k Air Gap in 3D Memory

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in achieving effective dielectric isolation with low dielectric constant in drain-select-level isolation structures, which affects the performance and efficiency of memory devices.

Innovation Solution

The implementation of a three-dimensional memory device structure that includes an alternating stack of insulating and electrically conductive layers, with a drain-select-level isolation structure having an effective dielectric constant less than 3.9, formed by filling a trench with a dielectric liner and air gap, and featuring memory opening fill structures with planar straight sidewalls in contact with the isolation structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dielectric materials are used in drain-select-level isolation structures, then the structure provides basic electrical isolation, but the dielectric constant is too high (greater than 3.9) which affects memory device performance and efficiency

Engineering Contradiction:
Improvedielectric isolation efficiencyVSAvoidisolation structure composition
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure employs a composite material system consisting of a dielectric liner layer (first dielectric material) and a dielectric fill material layer (second dielectric material with k-value less than 3.9). This composite approach allows the structure to achieve low effective dielectric constant while maintaining structural integrity and electrical isolation functionality, directly resolving the contradiction between isolation efficiency and material complexity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies different dielectric materials with different properties to different regions of the isolation structure. The dielectric liner provides structural stability and interface quality, while the dielectric fill material provides low-k properties for reduced capacitance. This local differentiation of material properties enables the structure to simultaneously achieve both mechanical reliability and electrical performance.

Inventive Principle:
Principle #3Local quality

2Productivity

If the dielectric constant of the isolation structure is reduced to improve memory device performance, then the dielectric isolation efficiency increases, but the manufacturing process becomes more complex requiring specific material deposition and patterning steps

Engineering Contradiction:
Improvememory device efficiencyVSAvoidisolation structure fabrication
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The dielectric liner is formed first as a preliminary step before filling with the low-k dielectric material. This preliminary action prepares the isolation trench with a structurally sound foundation that defines the final isolation structure boundaries, making subsequent filling and processing steps more straightforward and controllable.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structure fabrication is segmented into distinct steps: forming the dielectric liner, filling with low-k dielectric material, and selective removal of portions. This segmentation allows each step to be optimized independently, managing manufacturing complexity while achieving the desired low effective dielectric constant for improved device efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11871580B2Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
Publication Date: 2024.01.09 SANDISK TECHNOLOGIES LLC
  • US11871580B2 patent drawing
  • US11871580B2 patent drawing
  • US11871580B2 patent drawing

AI summary

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.