Drain Select Transistor Programming for Disturb-Susceptible Memory Strings
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Solution Overview
Problem
Existing semiconductor memory devices face issues with disturb phenomena affecting memory cells, leading to inefficiencies in programming select transistors and threshold voltage distributions.
Innovation Solution
A semiconductor memory device with control logic that detects disturb susceptible memory strings and cells through threshold voltage monitoring, performing additional program operations on drain select transistors to optimize threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a main program operation is performed on all drain select transistors, then programming coverage is improved, but disturb phenomena affect memory cells causing threshold voltage distribution degradation
Solution Approach 1:
The patent segments the programming operation into two distinct phases: a main program operation applied to all drain select transistors, and an additional program operation applied selectively to specific drain select transistors in disturb susceptible memory strings. This segmentation allows the system to achieve comprehensive programming coverage while avoiding uniform application of high-stress operations that cause disturb phenomena.
Solution Approach 2:
The patent applies local quality by performing additional program operations only on drain select transistors located in disturb susceptible memory strings, rather than uniformly across all transistors. The control logic identifies specific strings requiring additional programming based on their susceptibility to disturb, applying enhanced programming only where needed to maintain threshold voltage distribution without affecting other strings.
2Reliability
If additional program operations are performed on drain select transistors in disturb susceptible memory strings, then threshold voltage distribution is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by performing a threshold voltage monitoring operation on memory cells before the additional program operation. This monitoring identifies which memory strings are susceptible to disturb effects, allowing the control logic to pre-determine which drain select transistors require additional programming. This preliminary identification simplifies the subsequent programming process by providing a clear map of target strings.
Solution Approach 2:
The patent employs feedback through the threshold voltage monitoring operation that measures the state of memory cells and provides information to the control logic. This feedback mechanism allows the system to dynamically adjust programming operations based on actual threshold voltage conditions, identifying disturb susceptible strings and triggering additional program operations only where the monitoring indicates a need, thereby managing complexity through intelligent decision-making.
3Measurement precision
If threshold voltage monitoring operation is performed on memory cells, then disturb susceptible strings are detected, but operation time increases
Solution Approach 1:
The patent applies partial action by performing threshold voltage monitoring and additional program operations only on a subset of memory strings identified as disturb susceptible, rather than uniformly processing all strings. The control logic determines which specific strings require monitoring and additional programming based on their characteristics, applying these operations partially to only those strings where they are necessary, thereby reducing overall operation time while maintaining detection accuracy for problematic strings.
Data Source
AI summary
A semiconductor memory device, and a method of operation, includes a memory block including a plurality of memory strings. The semiconductor memory device also includes a peripheral circuit performing a main program operation on drain select transistors included in the memory block, and a test program operation and a threshold voltage monitoring operation on memory cells included in the memory block. The semiconductor memory device further includes control logic controlling the peripheral circuit to detect a disturb susceptible memory string, among the plurality of memory strings, based on a result of performing the threshold voltage monitoring operation on the memory cells, and to perform an additional program operation on a drain select transistor included in the disturb susceptible memory string.