Memory Cell Drain Silicide Segmentation for Leakage Reduction
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Solution Overview
Problem
Integrated circuits with memory cells experience gate-induced drain leakage due to repeated cycling, which compromises data storage as electrons build up between the drain and floating gate, leading to reduced electrical contact and memory cell failure.
Innovation Solution
Increasing the distance between the drain silicide and the floating gate while maintaining the same distance between the source silicide and the floating gate, achieved by forming a block over the drain silicide to terminate it at a blocked drain region, thereby reducing gate-induced drain leakage without compromising electrical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the drain silicide and the floating gate is increased to reduce gate induced drain leakage, then reliability is improved, but the area available for electrical contact is reduced
Solution Approach 1:
The drain structure is segmented into two distinct regions: a first drain region with a first silicide layer providing electrical contact, and a second drain region with a second silicide layer positioned farther from the floating gate to reduce GIDL. This segmentation allows each region to optimize its function independently, resolving the contradiction between contact area and GIDL resistance.
Solution Approach 2:
Different silicide layers are applied to different regions of the drain with different properties: the first silicide layer is positioned close to the floating gate for optimal electrical contact, while the second silicide layer is positioned farther away to minimize gate induced drain leakage. This local differentiation allows simultaneous optimization of both contact quality and GIDL resistance.
2Area of stationary object
If the area of the source is reduced to accommodate smaller integrated circuits, then device size is reduced, but electrical contact quality is compromised
Solution Approach 1:
The drain is segmented into functional regions with different silicide configurations, allowing the source area to be minimized for device scaling while the drain structure compensates by providing adequate electrical contact through its first silicide layer positioned close to the floating gate.
3Reliability
If different structures are created on the drain and source sides to address GIDL, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The second silicide layer is selectively applied only to the drain region where GIDL is a problem, rather than applying different structures to both source and drain. This partial action addresses the specific GIDL issue in the drain while maintaining manufacturing process simplicity by reusing the same silicide deposition process.
Data Source
AI summary
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a source, a drain, and a channel defined between the source and drain. A memory cell overlies the channel, where the memory cell includes a floating gate and a control gate overlying the floating gate. A block overlies a portion of the drain referred to as a blocked drain region, where the blocked drain region is adjacent to the channel. A drain silicide overlies the drain and terminates at the blocked drain region such that the blocked drain region is between the drain silicide and the channel.