Drain-Source Breakdown Junction for UIS-Robust Semiconductor Devices
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Solution Overview
Problem
Conventional power semiconductor devices face limitations in unclamped inductive switching (UIS) due to current crowding and filamentation, leading to potential device failure from thermal runaway and reduced UIS capability, particularly at the gate-drain PN junction.
Innovation Solution
Incorporating a drain-source breakdown junction into the semiconductor device design, allowing avalanche current to be carried through the drain-source path, thereby preferentially initiating breakdown at this junction instead of the drain-gate junction, and enhancing UIS capability without significantly affecting transconductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power semiconductor devices are designed with standard junction structures, then the device structure is simple and manufacturing is easier, but the device fails to withstand avalanche current properly due to current crowding and filamentation at the gate-drain junction
Solution Approach 1:
The device divides the current path into separate segments: the gate-drain junction handles normal operation while the drain-source breakdown junction handles avalanche current. This segmentation allows each junction to be optimized for its specific function, preventing current crowding at the gate-drain junction during avalanche events
Solution Approach 2:
The drain-source breakdown junction acts as an intermediary path that intercepts avalanche current before it reaches the gate-drain junction. By providing this intermediate breakdown path, the device redirects harmful avalanche current away from the vulnerable gate-drain junction, preventing thermal runaway
2Reliability
If the device allows avalanche breakdown at the drain-gate junction, then the breakdown mechanism is simple, but current crowding and filamentation occur leading to thermal runaway and device failure
Solution Approach 1:
The patent converts the potentially harmful avalanche breakdown phenomenon into a beneficial protective mechanism. By designing the drain-source breakdown junction to have a lower breakdown voltage than the gate-drain junction, avalanche current is intentionally directed through the drain-source path, transforming what would be a destructive event into a safe current dissipation mechanism
Solution Approach 2:
Instead of allowing breakdown at the conventional gate-drain junction, the invention inverts the breakdown location to the drain-source junction. This inversion changes the current flow path during avalanche events, distributing current more uniformly and preventing the current crowding that leads to thermal runaway
3Reliability
If a drain-source breakdown junction is added to the device, then UIS capability is enhanced, but the device structure becomes more complex with additional doped regions and isolation rings
Solution Approach 1:
The patent merges the avalanche protection function with the existing drain-source structure by adding a doped region and isolation ring that integrate with the conventional device architecture. The drain-source breakdown junction shares physical and functional elements with the normal device structure, reducing the overall complexity increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The drain-source breakdown junction design improves the device's ability to withstand avalanche current, reducing the risk of thermal runaway and enhancing UIS capability, thus increasing the device's reliability and performance.
Implementation Method 1
allowing avalanche current to be carried through the drain-source path, thereby preferentially initiating breakdown at this junction
Data Source
AI summary
A semiconductor device includes a semiconductor layer having an active region. The semiconductor layer has a first conductivity type. The semiconductor device further includes a plurality of alternating mesa stripes and trenches in the active region, a source metal layer electrically connected with the plurality of mesa stripes, an isolation ring adjacent the active region, the isolation ring having a second conductivity type opposite the first conductivity type, and a doped region in the semiconductor layer, wherein the isolation ring is between the active region and the doped region, the doped region having the second conductivity type and forming a P-N junction with the semiconductor layer. The source metal layer is electrically connected with the doped region.