DRAM Cell Sustaining Voltage Generator for Leakage Reduction
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Solution Overview
Problem
Conventional DRAM cell access transistors face a trade-off between high reliability and performance due to high threshold voltage and thick gate dielectric required for minimizing leakage current and sustaining high word-line voltage, leading to longer write times and incomplete signal restoration.
Innovation Solution
The introduction of a sustaining voltage generator that produces a voltage level higher than signal ONE or lower than signal ZERO, stored in the DRAM cell before the access transistor is turned off, allowing for extended storage capacitor sustainment even with leakage current through the access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the access transistor is designed with high threshold voltage to minimize leakage current, then the retention time of stored charges is improved, but the performance of the access transistor deteriorates
Solution Approach 1:
The patent applies preliminary action by bootstrapping the word line voltage before the access transistor needs to operate. The word line is pre-charged to a high voltage level (VPP) in advance, so when the access transistor turns on, it immediately has the full voltage swing needed for high-speed operation, eliminating the delay that would otherwise occur while the transistor charges up.
2Reliability
If the gate dielectric material is made thicker to sustain high word-line voltage, then the reliability of the access transistor is improved, but the performance of the access transistor deteriorates
Solution Approach 1:
The patent uses preliminary action by pre-charging the word line to high voltage before the access transistor operates. This allows the transistor to use a thicker gate dielectric for voltage sustainability while still achieving high drivability during operation, since the voltage is already established before the transistor switches.
Solution Approach 2:
The patent applies dynamics by making the word line voltage dynamic rather than static. The word line voltage switches between a high voltage level (VPP) during operation and a lower voltage level during standby, allowing the gate dielectric to be optimized for high voltage sustainability while maintaining high drivability when needed.
3Productivity
If the access transistor operates with high voltage swing to improve drivability, then the WRITE performance is improved, but the leakage current increases
Solution Approach 1:
The patent applies dynamics by making the word line voltage dynamic - high during WRITE operations to ensure proper transistor operation and data writing, then low during standby to minimize leakage current. This dynamic voltage adjustment allows the system to achieve both high WRITE performance and low leakage current at different times.
Data Source
AI summary
The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.