3D DRAM Cell and Peripheral Circuit Layout for Higher Integration
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Solution Overview
Problem
Existing DRAM devices face challenges in efficiently integrating word lines, bit lines, channels, and capacitors, which hinders the increase in integration degree.
Innovation Solution
A semiconductor device design with a substrate featuring first and second regions, including channels, gate structures, bit lines, capacitors, and source/drain patterns, where channels and gate structures are aligned at the same height, and circuit patterns are disposed in both upper and lower portions of the peripheral circuit region, enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channels and gate structures are arranged at different heights to simplify manufacturing, then manufacturing complexity is reduced, but integration density and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D arrangement to 3D vertical stacking, positioning memory cell channels and peripheral circuit channels at different heights (first height and second height respectively). This dimensional change enables simultaneous optimization of electrical characteristics through precise alignment while managing manufacturing complexity through structured multi-layer fabrication processes
2Quantity of substance
If circuit patterns are placed only in one location relative to memory cells, then manufacturing simplicity is maintained, but integration density and space utilization deteriorate
Solution Approach 1:
The patent utilizes vertical stacking to place peripheral circuit patterns both above and below the memory cell region in the third direction (vertical direction). This multi-level arrangement dramatically increases integration density by effectively utilizing three-dimensional space rather than being constrained to a single planar layer
Solution Approach 2:
The patent divides the substrate into distinct first and second regions, with memory cell channels in the first region and peripheral circuit channels in the second region. This spatial segmentation allows independent optimization of each circuit type while maintaining overall integration through controlled interconnections between regions
Data Source
AI summary
A semiconductor device may include a first channel on a first region of a substrate, a first gate structure surrounding a portion of the first channel, a bit line at a first side of the first channel and electrically connected to the first channel, a capacitor at a second side of the first channel and electrically connected to the first channel, a second channel on a second region of the substrate, a second gate structure surrounding a portion of the second channel, a first source/drain pattern at a first side of the second channel and electrically connected to the second channel, and a second source/drain pattern at a second side of the second channel and electrically connected to the second channel. Heights of the first and second channels from an upper surface of the substrate may be equal to each other.