DRAM Access Bus Dynamic Interleaving Mode Control
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Solution Overview
Problem
The existing bus storage architecture for accessing dynamic random access memory (DRAM) in application processors has limitations, including higher power consumption in low bandwidth scenarios, bus congestion due to inability to isolate access channels, and communication disparity across different Internet Protocols, especially when using a four-access channel interleaving mode.
Innovation Solution
A method and bus architecture that supports multiple interleaving modes and granularities by including additional fields in the access instruction to dynamically determine the access channel and address, allowing for flexible configuration of access channels to optimize power usage and bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four-access channel interleaving mode is used, then bandwidth utilization is improved, but power consumption increases in low bandwidth scenarios
Solution Approach 1:
The patent implements dynamic interleaving mode selection by adding control fields to the access instruction that specify the interleaving mode and granularity. The system can dynamically switch between 1-channel, 2-channel, 3-channel, and 4-channel interleaving modes based on real-time bandwidth requirements, allowing power consumption to be optimized for low bandwidth scenarios while maintaining high bandwidth utilization when needed
2Speed
If four-access channel interleaving mode is used, then access speed is improved, but bus congestion occurs due to inability to isolate access channels
Solution Approach 1:
The patent segments the four access channels into independently controllable units by introducing interleaving mode and granularity fields in the access instruction. This allows specific channels to be isolated or grouped based on traffic requirements, enabling selective channel usage that prevents bus congestion while maintaining access speed performance
3Use of energy by moving object
If single access channel is reserved, then power consumption is reduced, but address segments of other three access channels cannot be used
Solution Approach 1:
The patent enables dynamic channel allocation where the interleaving mode and granularity can be adjusted per access instruction. When a single channel is reserved for power saving, the system can dynamically allocate the remaining three channels to different address segments through configurable interleaving patterns, ensuring both power efficiency and continuous bandwidth utilization
Data Source
AI summary
Embodiments of the present disclosure provide a method and bus for accessing a dynamic random access memory (DRAM). The embodiments include receiving an access instruction, where the access instruction includes an access address, the access address includes a physical address, and a first field and a second field that are additionally set, the first field is used to indicate an interleaving mode, the interleaving mode indicates a manner of selecting an access channel, the second field is used to indicate an interleaving granularity, and the interleaving granularity indicates a capacity of an address space corresponding to the access channel; determining, according to the first field and the second field, the access channel and an address corresponding to the access channel; and accessing the DRAM according to the access channel and the address corresponding to the access channel.