DRAM Active Region Layout for Dense Cells and Electrical Isolation
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Solution Overview
Problem
The manufacturing process of dynamic random access memory (DRAM) devices has become increasingly complex due to the need for scaled-down chip sizes and higher cell densities, particularly in achieving buried word-line or buried bit-lines architectures.
Innovation Solution
A DRAM structure and method involving a substrate with alternating and staggered first and second active regions, where the second active regions have a tapering sidewall adjacent to trenches, and a specific etching and patterning process using self-aligned reverse patterning (SARP) to form the active regions and transfer patterns to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip size is scaled down and cell density is increased to achieve buried word-line or buried bit-lines architectures, then higher cell density is achieved, but manufacturing process complexity increases
Solution Approach 1:
The active regions are divided into two types (first active regions and second active regions) with different profile roughness characteristics. This segmentation allows different regions to serve different functional purposes, enabling high cell density while simplifying the overall manufacturing process by using a common patterning approach for both regions
Solution Approach 2:
Different profile roughness is introduced at different locations (first active regions vs. second active regions) to optimize local electrical characteristics. This local differentiation enables the structure to achieve both high density and manufacturing simplicity through targeted property variation
2Area of stationary object
If active regions are arranged at dense pitch for higher cell density, then chip size is reduced, but electrical isolation between active regions becomes more difficult to maintain
Solution Approach 1:
The invention applies different profile roughness characteristics to different active regions (first vs. second active regions) to locally optimize electrical isolation properties. This allows dense packing while maintaining reliable electrical isolation through targeted surface property variation at critical interfaces
Data Source
AI summary
A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.