Asymmetric DRAM Active Region Layout for Lower Drain Contact Resistance
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Solution Overview
Problem
As semiconductor integration levels increase, parasitic resistance between bitline contact holes and drain regions in DRAMs rises, reducing induction margins and charging/discharging speeds of storage capacitors.
Innovation Solution
The formation of active regions with a wordline structure that divides them into source and drain regions, where the drain region is larger than the source region, reducing parasitic resistance by increasing contact area and optimizing the arrangement of active regions in an array with shared wordline and bitline structures and isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the active region area is reduced to increase integration level, then device integration increases, but parasitic resistance between bitline contact holes and drain regions increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric active region where the drain region has a larger area than the source region. Specifically, the drain region extends further in the third direction (perpendicular to the second direction) to provide a larger contact area for the bitline contact hole. This local enlargement of the drain region reduces parasitic resistance at the critical bitline contact interface while maintaining overall compactness for high integration.
Solution Approach 2:
The patent employs asymmetry by designing the active region with unequal source and drain regions. The drain region is intentionally made larger than the source region in the third direction, creating an asymmetric structure that optimizes the contact area for bitline connections. This asymmetric design allows the drain to accommodate larger contact holes with lower resistance while the source maintains a compact footprint for high-density integration.
2Reliability
If the contact area is increased to reduce parasitic resistance, then parasitic resistance decreases, but device area increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric active region where the drain region has a larger area than the source region. Specifically, the drain region extends further in the third direction (perpendicular to the second direction) to provide a larger contact area for the bitline contact hole. This local enlargement of the drain region reduces parasitic resistance at the critical bitline contact interface while maintaining overall compactness for high integration.
Solution Approach 2:
The patent utilizes another dimension by extending the drain region in the third direction (perpendicular to the second direction where source and drain are arranged). This dimensional approach allows the drain region to achieve larger contact area without proportionally increasing the overall device footprint, as the extension occurs in a direction optimized for contact access rather than lateral expansion.
Data Source
AI summary
Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.