DRAM Address Error Detection with Controller-Verified EDC
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller. This allows for the detection and correction of errors in both address and data transmission, ensuring error-resistant operations by preventing erroneous write commands and optimizing system latency and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then productivity is improved, but signal quality deteriorates due to noise and transmission errors
Solution Approach 1:
The patent applies preliminary action by computing error-detection codes (EDC) for both address and data before transmission. The memory controller calculates EDC values for the address and data portions separately, then transmits them to the memory device. This allows error detection to be prepared in advance, enabling reliable detection even at high transfer rates where noise and interference are significant.
2Reliability
If error detection is performed on both address and data to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection process into two independent parts: address portion EDC and data portion EDC. Each portion is encoded separately with its own error-detection code, allowing the memory controller and memory device to handle and verify each independently. This segmented approach improves reliability for both address and data while managing complexity through modular, separate processing paths.
3Reliability
If address errors are detected and corrected to prevent data corruption, then reliability is improved, but latency increases due to verification time
Solution Approach 1:
The patent applies preliminary action by computing the address EDC in advance during the address setup phase, before the actual memory operation executes. The memory controller calculates the EDC for the address portion and transmits it along with the address, allowing the memory device to verify address integrity immediately upon receipt without adding significant latency to the critical memory access path.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.