DRAM Address Error Detection to Cancel Faulty Memory Writes
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code based on both address and data, which is then verified by the controller, allowing for the detection and prevention of erroneous write operations by canceling them, thereby ensuring error-resistant transmission of both address and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then data transmission speed is improved, but signal quality deteriorates due to noise and transmission errors
Solution Approach 1:
The patent applies preliminary action by computing error-detection codes for addresses before the actual memory write operation occurs. The controller calculates EDC codes for outgoing addresses, buffers them, and transmits them ahead of time. This allows error detection to be prepared in advance, enabling faster error identification without compromising signal quality at higher data transfer rates.
Solution Approach 2:
The patent introduces error-detection codes as an intermediary mechanism between the controller and memory device. These EDC codes serve as mediators that carry error detection information separately from the main data transmission, allowing the system to maintain high data transfer rates while independently verifying address integrity through dedicated error detection channels.
2Reliability
If error detection mechanisms are added to improve reliability, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges error detection functionality into the existing memory control architecture by integrating EDC code generation and verification into the controller's address handling pipeline. Rather than adding completely separate error detection systems, the solution combines address buffering, EDC calculation, and error verification into unified control logic that leverages existing memory management structures.
Solution Approach 2:
The controller's address buffer and processing logic serve multiple functions: normal address storage, EDC code generation, error detection verification, and coordination with memory timing. This multi-functionality reduces the need for dedicated error detection hardware, thereby limiting the increase in device complexity while maintaining enhanced error detection capabilities.
3Reliability
If address errors are detected and corrected to prevent data corruption, then data integrity is improved, but transmission latency increases
Solution Approach 1:
The patent reduces latency by performing error detection preparation in advance. EDC codes are calculated and buffered before the actual memory write operation, so that when data transmission occurs, error verification can proceed immediately without adding significant delay. This preliminary computation of error detection codes ensures data integrity while minimizing impact on transmission timing.
Solution Approach 2:
The error detection process operates continuously alongside normal memory operations rather than interrupting the data flow. The controller continuously generates and verifies EDC codes for addresses in the pipeline, allowing error detection to proceed in parallel with memory operations, thereby maintaining continuous useful action without significant latency penalties.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.