DRAM Address Error Coding Without Extra Parity Lines
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Solution Overview
Problem
Existing DDR3 SDRAM systems lack effective mechanisms to protect the integrity of address bits transmitted over the address bus, as they typically only provide error protection for data via the error code bus, leaving address data vulnerable to corruption.
Innovation Solution
A system and method that generates and stores an error code based on both the data and address, using an error code bus to protect both data and address bits between the memory and memory controller, without requiring additional address parity or error lines, utilizing an error code module to detect and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error codes are generated based on both data and address, then address protection is improved, but device complexity increases
Solution Approach 1:
The error code mechanism is designed to serve multiple functions: it protects both data and address simultaneously, and can operate in different modes (data protection only, address protection only, or both). This multi-functionality resolves the contradiction by making the same hardware infrastructure serve multiple protection needs without proportionally increasing complexity.
Solution Approach 2:
The system allows dynamic configuration of error code generation parameters, including selecting which bits of address and data to include in the error code calculation, and choosing between different protection modes. This parameter flexibility enables the system to adapt the level of protection to specific needs, balancing reliability requirements against complexity constraints.
2Reliability
If error code bus is used to protect both data and address, then protection coverage is improved, but loss of information increases due to additional error code transmission
Solution Approach 1:
The error code mechanism uses partial action by allowing selective protection modes where error codes are generated based on only certain portions of the address and data. This enables the system to provide protection coverage where needed while minimizing the overhead on bandwidth-utilizing channels, thus resolving the contradiction between comprehensive protection and information loss.
3Device complexity
If address parity lines are made unused, then device complexity is reduced, but reliability of address protection deteriorates
Solution Approach 1:
The error code bus acts as an intermediary mechanism that provides address protection functionality without requiring dedicated address parity lines. By using the existing error code infrastructure to mediate the protection function, the system achieves reliability without adding the physical complexity of separate parity wiring.
Data Source
AI summary
In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.