DRAM Address Error Detection to Prevent Corrupted Writes
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller. This allows for the detection and prevention of erroneous write operations by canceling them if errors are detected, ensuring both error-resistant data and address transmission. The DRAM can compute the EDC as soon as the address is received, and the controller can withhold data transmission until the EDC is confirmed, optimizing latency and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then memory system speed is improved, but signal quality deteriorates due to noise and transmission errors
Solution Approach 1:
The patent applies preliminary action by computing the error-detection code at the DRAM as soon as the address is received, before the actual data transfer completes. This allows the memory controller to verify integrity early and cancel erroneous operations before they corrupt data, thus maintaining high transfer rates while improving reliability through preemptive error detection
Solution Approach 2:
The patent implements feedback by having the DRAM compute and return an error-detection code to the memory controller, which then verifies this code against the transmitted address and data. This closed-loop feedback mechanism enables real-time detection of transmission errors without reducing the overall data transfer rate, resolving the contradiction between speed and reliability
2Loss of time
If error detection code computation is performed early to reduce latency, then response time is improved, but buffering requirements increase
Solution Approach 1:
The patent reduces latency by performing the error-detection code computation as soon as the address is received at the DRAM, before the full data transfer sequence completes. This preliminary action allows early verification and potential cancellation of erroneous operations, minimizing the time loss without requiring extensive buffering of data or addresses
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation